AS8C801800

256K X 36, 512K X 18 3.3V Synchronous SRAMs AS8C803600 3.3V I/O, Burst Counter AS8C801800 Pipelined Outputs, Single Cycle Deselect Features 256K x 36, 512K x 18 memory configurations Supports high system speed: – 150MHz 3.8ns clock access time ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP) Description The 256K x 36 / 512K x 18. The SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the AS8C803600/801800 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The AS8C803600...