AS7C4096A

February 2006 ® AS7C4096A 5.0V 512K × 8 CMOS SRAM Features Pin compatible to AS7C4096 Industrial and commercial temperature Organization: 524,288 words × 8 bits Center power and ground pins High speed - 10/12/15/20 ns address access time - 5/6 ns output enable access time Equal access and cycle times Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O JEDEC standard packages ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA - 400 mil 36-pin SOJ - 44-pin TSOP 2 Low power consumption: ACTIVE - 880mW/max @ 10 ns Low power consumption: STANDBY - 55mW/max CMOS Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1 Pin arrangements 36-pin SOJ (400 mil) A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC NC NC A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 NC NC 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC NC NC Row decoder 524,288 × 8 Array (4,194,304) Sense amp I/O8 Column decoder A10 A11 A12 A13 A14 A15 A16 A17 A18 WE OE CE Control Circuit Selection guide Maximum address access time Maximum outputenable access time Maximum operati...