AS7C1026C

September 2006 A AS7C1026C ® 5 V 64K X 16 CMOS SRAM Industrial (-40o to 85oC) temperature Organization: 65,536 words × 16 bits Center power and ground pins for low noise High speed - 15 ns address access time - 6 ns output enable access time Low power consumption via chip deselect Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O Upper and Lower byte pin Features JEDEC standard packaging ESD protection > _ 2000 volts - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 Pin arrangement 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Logic block diagram A1 A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 Address decoder A0 VCC I/O buffer Control circuit Address decoder A8 A9 A10 A11 A12 A13 A14 A15 WE UB OE LB CE 12/5/06, v 1.0 Alliance Memory AS7C1026C 65,536 x 16 Array GND P. 1 of 9 Copyright © Alliance Memory. All rights reserved. AS7C1026C ® Equal address access and cycle times (tAA, tRC, tWC) of 15 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications. When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is rea...