AS5SS512K36D

SSRAM AS5SS512K36 512K x 36 SSRAM Flow-Through SRAM No Bus Latency 100 99 PIN ASSIGNMENT (Top View) 100-Pin TQFP (DQ) BWD BWC BWB BWA CE1 CE2 CE3 VDD VSS CEN CLK WE OE ADV/LD A 82 A A A A A 81 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 MIL-STD-883 FEATURES Pin compatible and functionally equivalent to ZBT devices. Supports 133MHz bus operations with zero wait states -Data is transferred on every clock Internally self-timed output buffer control to eliminate the need to use asynchronous OE\ Registered inputs for Flow-Through operation Byte Write capability Common I/O architecture Fast clock-to-output times -6.5ns (for 133 MHz device)* -8.5ns (for 100 MHz device) Single 3.3V -5% and +1-% power supply VDD Separate VDD for 3.3V or 2.5V I/O Clock Enable (CEN\) pin to suspend operation Synchronous self-timed writes Available in 100-pin TSOP package.** Burst Capability - linear or interleaved burst order No bus latency architecture eliminated dead cycles between write and read cyccles BYTE C BYTE D DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 83 AVAILABLE AS MILITARY SPECIFICATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1371D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQ...