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AS4C8M16S Dataheets PDF



Part Number AS4C8M16S
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 128M - 8M x 16 bit Synchronous DRAM
Datasheet AS4C8M16S DatasheetAS4C8M16S Datasheet (PDF)

AS4C8M16S 128M - 8M x 16 bit Synchronous DRAM (SDRAM) Confidential Features Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function  Auto Refresh and Self Refresh  4096 refresh cycles/64ms  CKE power down mode  Single +3.3V  0.3V power supply .

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AS4C8M16S 128M - 8M x 16 bit Synchronous DRAM (SDRAM) Confidential Features Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function  Auto Refresh and Self Refresh  4096 refresh cycles/64ms  CKE power down mode  Single +3.3V  0.3V power supply  Interface: LVTTL  Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C) - Automotive A2 (-40 ~ 105°C) 54-pin 400 mil plastic TSOP II package   54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package All parts ROHS Compliant       (Rev. 2, Feb. /2014) Overview The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications. Table 1. Key Specifications AS4C16M16S tCK3 Clock Cycle time (min.) tAC3 Access time from CLK (max.) tRAS Row Active time (min.) tRC Row Cycle time (min.) Table 2. Ordering Information -6/7 6/7 ns 5.4/5.4 ns 42/42 ns 60/63 ns Part Number Frequency Package AS4C8M16S-7TCN 143 MHz 54 pin TSOP II AS4C8M16S-6TCN 166 MHz 54 pin TSOP II AS4C8M16S-6TIN 166 MHz 54 pin TSOP II AS4C8M16S-6BIN 166 MHz 54 ball TFBGA AS4C8M16S-7BCN 143 MHz 54 ball TFBGA AS4C8M16S-6TAN 166 MHz 54 pin TSOP II T : indicates TSOP II package B : indicates TFBGA package N : indicates Pb free and Halogen free – ROHS compliant parts C: Commercial I: Industrial A: Automotive temperatures Confidential 1 Rev. 2 Feb. /2014 AS4C8M16S Figure 1.1 Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE# CAS# RAS# CS# BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC/RFU UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Figure 1.2 Ball Assignment (Top View) 1 A B C D E F G H J VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 … 7 VDDQ VSSQ VDDQ VSSQ VDD CAS# BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM RAS# BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 WE# CS# A10 VDD Confidential 2 Rev. 2 Feb. /2014 AS4C8M16S Figure 2. Block Diagram CKE Row Decoder CLK CLOCK BUFFER 2M x 16 CELL ARRAY (BANK #A) Column Decoder CS# RAS# CAS# WE# DQ15 LDQM, UDQM Row Decoder A10/AP COLUMN COUNTER MODE REGISTER 2M x 16 CELL ARRAY (BANK #B) Column Decoder A0 A9 A11 BA0 BA1 ~ ADDRESS BUFFER REFRESH COUNTER Row Decoder 2M x 16 CELL ARRAY (BANK #C) Column Decoder Row Decoder 2M x 16 CELL ARRAY (BANK #D) Column Decoder Confidential 3 Rev. 2 Feb. /2014 ~ COMMAND DECODER CONTROL SIGNAL GENERATOR DQ Buffer DQ0 AS4C8M16S Pin Descriptions Table 3. Pin Details Symbol CLK Type Input Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Bank Activate: BA0, BA1 input select the bank for operation. BA1 0 0 1 1 A0-A11 Input BA0 0 1 0 1 Select Bank BANK #A BANK #B BANK #C BANK #D CKE Input BA0,BA1 In.


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