MT48H4M32LF

128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM Features Mobile Low-Power SDR SDRAM MT48H8M16LF – 2 Meg x 16 x 4 banks MT48H4M32LF – 1 Meg x 32 x 4 banks Features VDD/VDDQ = 1.7–1.95V Fully synchronous; all signals registered on positive edge of system clock Internal, pipelined operation; column address can be changed every clock cycle 4 internal banks for concurrent operation Programmable burst lengths (BL): 1, 2, 4, 8, and continuous Auto precharge, includes concurrent auto precharge Auto refresh and self refresh modes LVTTL-compatible inputs and outputs On-chip temperature sensor to control self refresh rate Partial-array self refresh (PASR) Deep power-down (DPD) Selectable output drive strength (DS) 64ms refresh period Options VDD/VDDQ: 1.8V/1.8V Addressing – Standard addressing option Configuration – 8 Meg x 16 (2 Meg x 16 x 4 banks) – 4 Meg x 32 (1 Meg x 32 x 4 banks) Plastic “green” packages – 54-ball VFBGA (8mm x 8mm)1 – 90-ball VFBGA (8mm x 13mm)2 Timing: cycle time – 6ns at CL = 3 – 7.5ns at CL = 3 Operating temperature range – Commercial (0˚C to +70˚C) – Industrial (–40˚C to +85˚C) Revision Notes: Marking H LF 8M16 4M32 B4 B5 -6 -75 None IT :K 1. Available only for x16 configuration. 2. Available only for x32 configuration. Table 1: Configuration Addressing Architecture Number of banks Bank address balls Row address balls Column address balls 8 Meg x 16 4 BA0, BA1 A[11:0] A[8:0] 4 Meg x 32 4 BA0, BA1 A[11:0] A[7:0] Table 2:...