MT46H4M32LF

128Mb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H8M16LF – 2 Meg x 16 x 4 Banks MT46H4M32LF – 1 Meg x 32 x 4 Banks Features VDD/VDDQ = 1.70–1.95V Bidirectional data strobe per byte of data (DQS) Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs 4 internal banks for concurrent operation Data masks (DM) for masking write data; one mask per byte Programmable burst lengths (BL): 2, 4, 8, or 16 Concurrent auto precharge option is supported Auto refresh and self refresh modes 1.8V LVCMOS-compatible inputs Temperature-compensated self refresh (TCSR) Partial-array self refresh (PASR) Deep power-down (DPD) Status read register (SRR) Selectable output drive strength (DS) Clock stop capability 64ms refresh Table 1: Key Timing Parameters (CL = 3) Speed Grade -5 -54 -6 -75 Clock Rate 200 MHz 185 MHz 166 MHz 133 MHz Access Time 5.0ns 5.0ns 5.0ns 6.0ns Options VDD/VDDQ – 1.8V/1.8V Configuration – 8 Meg x 16 (2 Meg x 16 x 4 banks) – 4 Meg x 32 (1 Meg x 32 x 4 banks) Row size option – JEDEC-standard option Plastic "green" package – 60-ball VFBGA (8mm x 9mm) 1 – 90-ball VFBGA (8mm x 13mm) 2 Timing – cycle time – 5ns @ CL = 3 (200 MHz) – 5.4ns @ CL = 3 (185 MHz) – 6ns @ CL = 3 (166 MHz) – 7.5ns @ CL = 3 (133 MHz) Operating tem...