NT5DS64M8DS

NT5DS64M8DS N2DS51216DS 512Mb DDR SDRAM Preliminary Feature CAS Latency Frequency DDR-333 DDR400  2KB page size for all configurations. Units Speed Sorts -6K CL-tRCD-tRP -5T  DQS is edge-aligned with data for reads and is center-aligned with data for WRITEs 2.5-3-3 266 333 333 3-3-3 266 333 400 tCK CL=2 Speed CL=2.5 CL=3  Differential clock inputs (CK and ) Mbps  Data mask (DM) for write data  DLL aligns DQ and DQS transition with CK transitions.  Commands entered on each positive CK edge; data  Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) and data mask referenced to both edges of DQS  Burst Lengths: 2, 4 or 8  Auto Pre-charge option for each burst access  Auto-Refresh and Self-Refresh Mode  7.8 µs max. Average Periodic Refresh Interval  2.5V (SSTL_2 compatible) I/O  RoHS and Halogen-Free compliance  Packages: 66 pin TSOPII     4 internal memory banks for concurrent operation. CAS Latency: 2, 2.5 and 3 Double Data Rate Architecture Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.  Commercial grade device support 0℃~70℃ Operating Temperature (-6K/5T) 1 REV 0.1 11/2012 NT5DS64M8DS N2DS51216DS 512Mb DDR SDRAM Preliminary Description Elixir 512Mb SDRAMs is a high-speed CMOS Double Data Rate SDRAM containing 536,870,912 bits. It is internally configured as a qual-bank DRAM. The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or...