H5MS2562JFR-J3M

256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb (16Mx16bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / July. 2009 1 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 1.0 1.1 1.2 - Initial Draft - IDD Specification updated - The final version - Insert DDR370 DC/AC Characteristics - Omit a typo in package information History Draft Date May 2008 May 2008 Nov. 2008 Apr. 2009 July. 2009 Remark Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / July. 2009 2 Mobile DDR SDRAM 256Mbit (16M x 16bit) H5MS2562JFR Series FEATURES SUMMARY ● Mobile DDR SDRAM clock cycle ● MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per ● Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address (Row address and Column address) ● CAS LATENCY - Programmable CAS latency 2 or 3 supported ● SUPPLY VOLTAGE - 1.8V device: VD...