Document
DATA SHEET
1G bits DDR2 SDRAM
EDE1108AJBG (128M words × 8 bits) EDE1116AJBG (64M words × 16 bits)
Specifications
• Density: 1G bits • Organization 16M words × 8 bits × 8 banks (EDE1108AJBG) 8M words × 16 bits × 8 banks (EDE1116AJBG) • Package 60-ball FBGA (EDE1108AJBG) 84-ball FBGA (EDE1116AJBG) Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate 800Mbps (max.) • 1KB page size (EDE1108AJBG) Row address: A0 to A13 Column address: A0 to A9 • 2KB page size (EDE1116AJBG) Row address: A0 to A12 Column address: A0 to A9 • Eight internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): Sequential (4, 8) Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Driver strength: normal, weak • Refresh: auto-refresh, self-refresh
Features
• Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation • Off-Chip Driver (OCD) impedance adjustment is not supported.
• Refresh cycles: 8192 cycles/64ms
Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C
Document No. E1732E21 (Ver.2.1) Date Published September 2011 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2010-2011
EDE1108AJBG, EDE1116AJBG
Ordering Information
Part number EDE1108AJBG-8E-F EDE1116AJBG-8E-F Die revision J Organization (words × bits) 128M × 8 64M × 16 Internal banks 8 Speed bin (CL-tRCD-tRP) DDR2-800 (5-5-5) DDR2-800 (5-5-5) Package 60-ball FBGA 84-ball FBGA
Part Number
E D E 11 08 A J BG - 8E - F
Elpida Memory Type D: Packaged Device Product Family E: DDR2 Density / Bank 11: 1Gb / 8-bank Organization 08: x8 16: x16 Power Supply, Interface A: 1.8V, SSTL_18
Environment code F: Lead Free (RoHS compliant) and Halogen Free Speed 8E: DDR2-800 (5-5-5)
Package BG: FBGA Die Rev.
Data Sheet E1732E21 (Ver.2.1)
2
EDE1108AJBG, EDE1116AJBG
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
84-ball FBGA
(×16 organization)
8
9
(×8 organization) 1
A
2
3
7
1 A
2
3
7
8
9
VDD NU/ /RDQS VSS
B
VSSQ /DQS VDDQ
VDD B
NC
VSS
VSSQ /UDQS VDDQ .