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H5PS1G83EFR Dataheets PDF



Part Number H5PS1G83EFR
Manufacturers Hynix
Logo Hynix
Description 1Gb DDR2 SDRAM
Datasheet H5PS1G83EFR DatasheetH5PS1G83EFR Datasheet (PDF)

H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1Gb DDR2 SDRAM H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Nov 2008 1 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Revision Details Rev. 0.1 0.2 0.3 0.4 Initial data sheet released IDD data Updated Editorial Correction (added S6) Editorial change on TOPER Hist.

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H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1Gb DDR2 SDRAM H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Nov 2008 1 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Revision Details Rev. 0.1 0.2 0.3 0.4 Initial data sheet released IDD data Updated Editorial Correction (added S6) Editorial change on TOPER History Draft Date May. 2008 Aug. 2008 Sep. 2008 Nov. 2008 Rev. 0.4 / Nov 2008 2 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Operating Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions(SSTL_1.8) 3.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC Output Parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 0.4 / Nov 2008 3 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • • • • • • • • • • • • • • • • • • • • • • • • • • VDD = 1.8 +/- 0.1V VDDQ = 1.8 +/- 0.1V All inputs and outputs are compatible with SSTL_18 interface 8 banks Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 3, 4, 5 and 6 supported Programmable additive latency 0, 1, 2, 3, 4 and 5 supported Programmable burst length 4/8 with both nibble sequential and interleave mode Internal eight bank operations with single pulsed RAS Auto refresh and self refresh supported tRAS lockout supported 8K refresh cycles /64ms JEDEC standard 60ball FBGA(x4/x8), 84ball FBGA(x16) Full strength driver option controlled by EMR On Die Termination supported Off Chip Driver Impedance Adjustment supported Read Data Strobe supported (x8 only) Self-Refresh High Temperature Entry Ordering Information Part No. H5PS1G43EFR-XX* H5PS1G83EFR-XX* H5PS1G63EFR-XX* Note: Configuration Package 256Mx4 128Mx8 64Mx16 84 Ball 60 Ball Operating Frequency Grade E3 C4 Y5 S6 S5 tCK(ns) 5 3.75 3 2.5 2.5 CL 3 4 5 6 5 tRCD 3 4 5 6 5 tRP 3 4 5 6 5 Unit Clk Clk Clk Clk Clk -XX* is the speed bin, refer to the Operating Frequency table for complete part number. Hynix lead & halogen-free products are compliant to RoHS. Rev. 0.4 / Nov 2008 4 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 1.2 Pin Configuration & Address Table 256Mx4 DDR2 Pin Configuration(Top view: see balls through package) 1 2 3 7 8 9 VDD NC VDDQ NC VDDL NC VSSQ DQ1 VSSQ VREF CKE VSS DM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13 VDDQ NC VDDQ NC VDD ODT BA2 BA0 A10 VDD VSS A3 A7 VSS VDD A12 ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size Rev. 0.4 / Nov 2008 256Mx4 8 BA0,BA1,BA2 A10/AP A0 - A13 A0-A9, A11 1 KB 5 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 128Mx8 DDR2 PIN CONFIGURATION(Top view: see balls through package) 1 2 3 7 8 9 VDD DQ6 VDDQ DQ4 VDDL NU/RDQS VSSQ DQ1 VSSQ VREF CKE VSS DM/RDQS VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13 VDDQ DQ7 VDDQ DQ5 VDD ODT BA2 BA0 A10 VDD VSS A3 A7 VSS VDD A12 ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size 128Mx8 8 BA0, BA1, BA2 A10/AP A0 - A13 A0-A9 1 KB Rev. 0.4 / Nov 2008 6 H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR 64Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package) 1 2 3 7 8 9 VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC, A14 A B C D E F G H J K L M N P R VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC, A15 UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 .


H5PS1G43EFR H5PS1G83EFR H5PS1G63EFR


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