MT46H256M32R4

2Gb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H128M16LF – 32 Meg x 16 x 4 Banks MT46H64M32LF – 16 Meg x 32 x 4 Banks MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4 MT46H256M32R4 – 32 Meg x 16 x 4 Banks x 4 Features VDD/VDDQ = 1.70–1.95V Bidirectional data strobe per byte of data (DQS) Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs 4 internal banks for concurrent operation Data masks (DM) for masking write data; one mask per byte Programmable burst lengths (BL): 2, 4, 8, or 16 Concurrent auto precharge option is supported Auto refresh and self refresh modes 1.8V LVCMOS-compatible inputs Temperature-compensated self refresh (TCSR) Partial-array self refresh (PASR) Deep power-down (DPD) Status read register (SRR) Selectable output drive strength (DS) Clock stop capability 64ms refresh; 32ms for the automotive temperature range Table 1: Key Timing Parameters (CL = 3) Speed Grade -5 -54 -6 -75 Clock Rate 200 MHz 185 MHz 166 MHz 133 MHz Access Time 5.0ns 5.0ns 5.0ns 6.0ns Options VDD/VDDQ – 1.8V/1.8V Configuration – 128 Meg x 16 (32 Meg x 16 x 4 banks) – 64 Meg x 32 (16 Meg x 32 x 4 banks) Addressing – JEDEC-standard – Reduced page-size1 – 4-die stack reduced page-size2 – 2-die ...