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H5PS2562GFR-xxL Dataheets PDF



Part Number H5PS2562GFR-xxL
Manufacturers Hynix
Logo Hynix
Description 256Mb DDR2 SDRAM
Datasheet H5PS2562GFR-xxL DatasheetH5PS2562GFR-xxL Datasheet (PDF)

H5PS2562GFR Series 256Mb DDR2 SDRAM H5PS2562GFR-xxC H5PS2562GFR-xxI H5PS2562GFR-xxL H5PS2562GFR-xxJ This document is a general product description and is subject to change without notice. SK hynix Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3 / June. 2012 1 H5PS2562GFR series Revision History Rev. 1.0 1.1 1.2 1.3 History Release Corrected Typo Corrected Typo New revised logo Draft Date Nov. 2010 Dec. 2010 Feb.2011 June.2012 Re.

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H5PS2562GFR Series 256Mb DDR2 SDRAM H5PS2562GFR-xxC H5PS2562GFR-xxI H5PS2562GFR-xxL H5PS2562GFR-xxJ This document is a general product description and is subject to change without notice. SK hynix Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3 / June. 2012 1 H5PS2562GFR series Revision History Rev. 1.0 1.1 1.2 1.3 History Release Corrected Typo Corrected Typo New revised logo Draft Date Nov. 2010 Dec. 2010 Feb.2011 June.2012 Rev.1.3 / June. 2012 2 H5PS2562GFR series Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev.1.3 / June. 2012 3 H5PS2562GFR series 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 2, 3, 4, 5, 6 and 7 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4 / 8 with both nibble sequential and interleave mode • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 84ball FBGA(x16) : 7.5mm x 12.5mm • Full strength driver option controlled by EMRS • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Self-Refresh High Temperature Entry • Partial Array Self Refresh support Rev.1.3 / June. 2012 4 H5PS2562GFR series Ordering Information Part No. H5PS2562GFR-xx*C H5PS2562GFR-xx*I H5PS2562GFR-xx*L 16Mx16 Configuration Power Consumption Normal Consumption Normal Consumption Low Power Consumption (IDD6 Only) Low Power Consumption (IDD6 Only) Operation Temp Commercial Industrial Commercial 84 Ball fBGA Package H5PS2562GFR-xx*J Note: Industrial -XX* is the speed bin, refer to the Operating Frequency table for complete part number. - SK hynix Inc. Halogen-free products are compliant to RoHS. SK hynix Inc. supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materials. We'll add "R" character after "F" for Lead & Halogen free products Operating Frequency Grade E3 C4 Y5 S6 S5 G7 Note: -G7 is a special speed product used in electronic engineering for high speed storage of the working data of a consumer digital electronic device. tCK(ns) 5 3.75 3 2.5 2.5 1.875 CL 3 4 5 6 5 7 tRCD 3 4 5 6 5 7 tRP 3 4 5 6 5 7 Unit Clk Clk Clk Clk Clk Clk Rev.1.3 / June. 2012 5 H5PS2562GFR series 1.2 Pin Configuration & Address Table 16Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package) 3 VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L M N P R 7 VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC 8 UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC VSS VDD 9 VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT 1 VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL 2 NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE NC BA0 A10 VSS A3 A7 VDD A12 ROW AND COLUMN ADDRESS TABLE ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size 16Mx16 4 BA0, BA1 A10/AP A0 - A12 A0-A8 1 KB Rev.1.3 / June. 2012 6 H5PS2562GFR series 1.3 PIN DESCRIPTION PIN TYPE DESCRIPTION Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and outpu.


H5PS2562GFR-xxI H5PS2562GFR-xxL H5PS2562GFR-xxJ


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