SEP02G72E2BF2SA-30R

Data Sheet Rev.1.0 23.11.2010 2GB DDR2 – SDRAM registered DIMM Features: 240 Pin RDIMM SEP02G72E2BF2SA-30R 2GB PC2-5300 in FBGA Technology RoHS compliant           240-pin 72-bit DDR2 registered Dual-In-Line Double Data Rate Synchronous DRAM Module for server applications Module organization: dual rank 256M x 72 VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V 1.8V I/O ( SSTL_18 compatible) Serial Presence Detect with EEPROM Supports ECC error detection and correction JEDEC compatible DDR2 PLL/Register component with parity bit support for address and control bus Gold-contact pad This module family is fully pin and functional compatible to JEDEC. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR2 SDRAM component Samsung K4T1G084QF 128Mx8 DDR2 SDRAM in FBGA-60 package Four bit prefetch architecture Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency – 1 tCK Programmable burst length: 4 or 8 Adjustable data-output drive strength On-die termination (ODT) DLL to align DQ and DQS transitions with CK Options:  Data Rate / Latency DDR2 533 MTs / CL4 DDR2 667 MT/s / CL5 Marking -37 -30  Module Density 2048MB with 18 dies and 2 ranks Standard Grade (TA) (TC) 0°C to 70°C 0°C to 85°C            Environmental Requirements:       Operating temperature (TAMBIENT) Standard Grade 0°C to 70°C Operati...