SEC04G72C1BC2MT-30R

preliminary Data Sheet Rev.0.9 27.08.2012 4GB DDR2 – SDRAM SO-DIMM Features: 200 Pin SO-CDIMM SEC04G72C1BC2MT-xxR 4GB PC2-5300 in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR2 667 MT/s CL5 DDR2 533 MT/s CL4  Module Density 4096MB with 18 dies and 2 ranks Standard Grade (TA) (TC) 0°C to 70°C 0°C to 85°C Marking -30 -37           200-pin 72-bit Small Outline Clocked Dual-In-Line Double Data Rate Synchronous DRAM Module Module organization: dual rank 512M x 72 VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V 1.8V I/O ( SSTL_18 compatible) Serial Presence Detect with EEPROM Phase-lock loop (PLL) clock driver to reduce loading Supports ECC error detection and correction Gold-contact pad This module is fully pin and functional compatible to the JEDEC PC2-6400 spec. and JEDEC- Standard MO-224. (see www.jedec.org) The PCB and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR2 - SDRAM component Micron MT47H256M8EB-25E:C 256Mx8 DDR2 SDRAM in FBGA-60 package Four bit prefetch architecture DLL to align DQ and DQS transitions with CK Eight internal device banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency – 1 tCK Programmable burst length: 4 or 8 Adjustable data-output drive strength On-die termination (ODT)             Environmental Requirements:  Operating temperature (ambient) St...