N-Channel Logic Level Enhancement Mode Field Effect Transistor
Description
S T U/D420S
S amHop Microelectronics C orp.
J uly 05 , 2006
N-C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V DS S
40V
F E AT UR E S
( mW)
ID
24A
R DS (ON)
Max
S uper high dense cell design for low R DS (ON ).
24 @ V G S = 10V 30 @ V G S = 4.5V
R ugged and reliable. TO-252 and TO-251 P ackage.
D
D G S
G D
S
...
