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HYMP125U64CP8-Y5 Dataheets PDF



Part Number HYMP125U64CP8-Y5
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version
Datasheet HYMP125U64CP8-Y5 DatasheetHYMP125U64CP8-Y5 Datasheet (PDF)

240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchrnous DRAMs (.

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240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) • • • • • • • Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(128Mx8), 84ball FBGA(64Mx16) 133.35 x 30.00 mm form factor RoHS compliant • • • • • • • ORDERING INFORMATION Part Name HYMP164U64CP6-C4/Y5/S6/S5 HYMP164U64CR6-C4/Y5/S6/S5 HYMP112U64CP8-C4/Y5/S6/S5 HYMP112U64CR8-C4/Y5/S6/S5 HYMP112U72CP8-C4/Y5/S6/S5 HYMP125U64CP8-C4/Y5/S6/S5 HYMP125U64CR8-C4/Y5/S6/S5 HYMP125U72CP8-C4/Y5/S6/S5 Density 512MB 512MB 1GB 1GB 1GB 2GB 2GB 2GB Org. 64Mx64 64Mx64 128Mx64 128Mx64 128Mx72 256Mx64 256Mx64 256Mx72 # of DRAMs 4 4 8 8 9 16 16 18 # of ranks 1 1 1 1 1 2 2 2 Materials Lead-free Halogen-free Lead-free Halogen-free Lead-free Lead-free Halogen-free Lead-free ECC None None None None ECC None None ECC This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Jul. 2008 1 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK ADDRESS TABLE Density 512MB 1GB 1GB 2GB 2GB Organization Ranks 64M x 64 128M x 64 128M x 72 256M x 64 256M x 72 1 1 1 2 2 SDRAMs 64Mb x 16 128Mb x 8 128Mb x 8 128Mb x 8 128Mb x 8 # of DRAMs 4 8 9 16 18 # of row/bank/column Address 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms Rev. 0.6 / Jul. 2008 2 1240pin DDR2 SDRAM Unbuffered DIMMs Input/Output Functional Description Symbol CK[2:0], CK[2:0] Type SSTL Polarity Differential Crossing Pin Description CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data is reference to the crossing of CK and.


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