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HYMP125U72CP8-S6 Dataheets PDF



Part Number HYMP125U72CP8-S6
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version
Datasheet HYMP125U72CP8-S6 DatasheetHYMP125U72CP8-S6 Datasheet (PDF)

240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchrnous DRAMs (.

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240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) • • • • • • • Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(128Mx8), 84ball FBGA(64Mx16) 133.35 x 30.00 mm form factor RoHS compliant • • • • • • • ORDERING INFORMATION Part Name HYMP164U64CP6-C4/Y5/S6/S5 HYMP164U64CR6-C4/Y5/S6/S5 HYMP112U64CP8-C4/Y5/S6/S5 HYMP112U64CR8-C4/Y5/S6/S5 HYMP112U72CP8-C4/Y5/S6/S5 HYMP125U64CP8-C4/Y5/S6/S5 HYMP125U64CR8-C4/Y5/S6/S5 HYMP125U72CP8-C4/Y5/S6/S5 Density 512MB 512MB 1GB 1GB 1GB 2GB 2GB 2GB Org. 64Mx64 64Mx64 128Mx64 128Mx64 128Mx72 256Mx64 256Mx64 256Mx72 # of DRAMs 4 4 8 8 9 16 16 18 # of ranks 1 1 1 1 1 2 2 2 Materials Lead-free Halogen-free Lead-free Halogen-free Lead-free Lead-free Halogen-free Lead-free ECC None None None None ECC None None ECC This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.6 / Jul. 2008 1 1240pin DDR2 SDRAM Unbuffered DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK ADDRESS TABLE Density 512MB 1GB 1GB 2GB 2GB Organization Ranks 64M x 64 128M x 64 128M x 72 256M x 64 256M x 72 1 1 1 2 2 SDRAMs 64Mb x 16 128Mb x 8 128Mb x 8 128Mb x 8 128Mb x 8 # of DRAMs 4 8 9 16 18 # of row/bank/column Address 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms Rev. 0.6 / Jul. 2008 2 1240pin DDR2 SDRAM Unbuffered DIMMs Input/Output Functional Description Symbol CK[2:0], CK[2:0] Type SSTL Polarity Differential Crossing Pin Description CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data is reference to the crossing of CK and /CK (Both directions of crossing) Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the CKE[1:0] SSTL Active High S[1:0] SSTL Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 RAS, CAS, WE ODT[1:0] SSTL SSTL Supply Supply SSTL Active Low Active High /RAS,/CAS and /WE(ALONG WITH S) define the command being entered. Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Vref VDDQ BA[2:0] - Selects which DDR2 SDRAM internal bank of four or eight is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA15) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to A[9:0], A10/AP, A[13:11] SSTL - the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ[63:0], CB[7:0] SSTL - Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input dat.


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