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M2N2G64TU8HG5B Dataheets PDF



Part Number M2N2G64TU8HG5B
Manufacturers Nanya
Logo Nanya
Description Unbuffered DDR2 SO-DIMM
Datasheet M2N2G64TU8HG5B DatasheetM2N2G64TU8HG5B Datasheet (PDF)

M2N1G64TUH8G5F / M2S1G64TUH8G4F / M2N2G64TU8HG5B / M2N2G64TU8HG4B 1GB: 128M x 64 / 2GB: 256M x 64 PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Based on DDR2-667/800 64Mx16 (1GB)/128Mx8 (2GB) SDRAM G-Die Features • Performance: Speed Sort DIMM CAS Latency fck – Clock Freqency tck – Clock Cycle Data Transfer Speed PC2-5300 -3C 5 333 3 667 PC2-6400 -AC 5 400 2.5 800 MHz ns Mbps • Automatic and controlled precharge commands • Programmable Operation: - DIMM  Latency: 3, 4, 5 - Burst Type: Sequenti.

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M2N1G64TUH8G5F / M2S1G64TUH8G4F / M2N2G64TU8HG5B / M2N2G64TU8HG4B 1GB: 128M x 64 / 2GB: 256M x 64 PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Based on DDR2-667/800 64Mx16 (1GB)/128Mx8 (2GB) SDRAM G-Die Features • Performance: Speed Sort DIMM CAS Latency fck – Clock Freqency tck – Clock Cycle Data Transfer Speed PC2-5300 -3C 5 333 3 667 PC2-6400 -AC 5 400 2.5 800 MHz ns Mbps • Automatic and controlled precharge commands • Programmable Operation: - DIMM  Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write • 13/10/2 Addressing (1GB) • 14/10/2 Addressing (2GB) • 7.8 s Max. Average Periodic Refresh Interval • Serial Presence Detect • Gold contacts • 1GB module’s SDRAMs are 84-ball BGA Package • 2GB module’s SDRAMs are 60-ball BGA Package • RoHS compliance Unit • 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) • 1GB: 128Mx64 Unbuffered DDR2 SO-DIMM based on 64M x16 DDR2 SDRAM G-Die devices. • 2GB: 256Mx64 Unbuffered DDR2 SO-DIMM based on 128M x8 DDR2 SDRAM G-Die devices. • Intended for 333MHz and 400MHz applications • Inputs and outputs are SSTL-18 compatible • VDD = VDDQ = 1.8V ± 0.1V • SDRAMs have 8 internal banks for concurrent operation • Differential clock inputs • Data is read or written on both clock edges • DRAM DLL aligns DQ and DQS transitions with clock transitions. • Address and control signals are fully synchronous to positive clock edge • Auto Refresh (CBR) and Self Refresh Modes Description M2N1G64TUH8G5F / M2S1G64TUH8G4F / M2N2G64TU8HG5B / M2N2G64TU8HG4B are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 128Mx64 (1GB)/256Mx64 (2GB) high-speed memory array. M2N1G64TUH8G5F / M2S1G64TUH8G4F uses eight 64Mx16 84-ball BGA packaged devices and M2N2G64TU8HG5B / M2N2G64TU8HG4B uses sixteen 128Mx8 60-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir DDR2 SODIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint. The DIMM is intended for use in applications operating of 333MHz/400MHz clock speeds and achieves high-speed data transfer speed of 667Mbps/800Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A12 (1GB) / A0-A13 (2GB) and I/O inputs BA0, BA1 and BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 07/2010 1 NANYA reserves the right to change products and specifications without notice. © NANYA TECHNOLOGY CORPORATION M2N1G64TUH8G5F / M2S1G64TUH8G4F / M2N2G64TU8HG5B / M2N2G64TU8HG4B 1GB: 128M x 64 / 2GB: 256M x 64 PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Ordering Information Part Number M2N2G64TU8HG5B-AC M2N2G64TU8HG5B-3C M2N2G64TU8HG4B-AC M2N1G64TUH8G5F-AC M2N1G64TUH8G5F-3C M2S1G64TUH8G4F-AC DDR2-800 DDR2-667 DDR2-800 DDR2-800 DDR2-667 DDR2-800 Speed PC2-6400 PC2-5300 PC2-6400 PC2-6400 PC2-5300 PC2-6400 400MHz (2.5ns @ CL = 5) 333MHz (3.0ns @ CL = 5) 400MHz (2.5ns @ CL = 5) 1.8V 400MHz (2.5ns @ CL = 5) 333MHz (3.0ns @ CL = 5) 400MHz (2.5ns @ CL = 5) 128Mx64 Gold 256Mx64 Organization Power Leads Note Pin Description CK0, CK1, ,  Differential Clock Inputs CKE0, CKE1    ,  A0-A9 A11-A13 A0-A9 A10/AP BA0, BA1, BA2 ODT0, ODT1 NC Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Row Address Inputs Column Address Inputs Column Address Input/Auto-precharge SDRAM Bank Address Inputs Active termination control lines No Connect DQ0-DQ63 DQS0-DQS7 - DM0-DM7 VDD VREF VDDSPD VSS SCL SDA SA0, SA1 Data input/output Bidirectional data strobes Differential data strobes Input Data Masks Power (1.8V) Ref. Voltage for SSTL_18 inputs Serial EEPROM positive power supply Ground Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Note: A13 is for 2GB modules only. REV 1.0 07/2010 2 NANYA reserves the right to change products and specifications without notice. © NANYA TECHNOLOGY CORPORATION M2N1G64TUH8G5F / M2S1G64TUH8G4F / M2N2G64TU8HG5B / M2N2G64TU8HG4B 1GB: 128M x 64 / 2GB: 256M x 64 PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Pinout Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VREF VSS DQ0 DQ1 VSS  DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS  DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS  Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0  VSS DQ14 DQ15 VSS VSS DQ20.


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