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HYMP512S64CP8-Y5 Dataheets PDF



Part Number HYMP512S64CP8-Y5
Manufacturers Hynix
Logo Hynix
Description 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb
Datasheet HYMP512S64CP8-Y5 DatasheetHYMP512S64CP8-Y5 Datasheet (PDF)

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver. This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 S.

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200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver. This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & CK) • • • • • • • Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball(x8), 84ball(x16) FBGA 67.60 x 30.00 mm form factor Lead-free Products are RoHS compliant • • • • • ORDERING INFORMATION Part Name HYMP532S64CP6-E3/C4/Y5/S5/S6 HYMP564S64CP6-E3/C4/Y5/S5/S6 HYMP512S64CP8-E3/C4/Y5/S5/S6 HYMP532S64CLP6-E3/C4/Y5/S5/S6 HYMP564S64CLP6-E3/C4/Y5/S5/S6 HYMP512S64CLP8-E3/C4/Y5/S5/S6 Density 256MB 512MB 1GB 256MB 512MB 1GB Organization 32Mx64 64Mx64 128Mx64 32Mx64 64Mx64 128Mx64 # of DRAMs 4 8 16 4 8 16 # of ranks 1 2 2 1 2 2 Materials Lead free* Lead free Lead free Lead free Lead free Lead free Power Consumption Normal Normal Normal Low Low Low Notes: 1. All Hynix’ DDR2 Lead-free parts are compliant to RoHS. This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Jul. 2007 1 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) Speed @CL3 Speed @CL4 Speed @CL5 Speed @CL6 CL-tRCD-tRP 400 533 3-3-3 C4 (DDR2-533) 533 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 5-5-5 S5 (DDR2-800) 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK ADDRESS TABLE Density 256MB 512MB 1GB Organization Ranks 32M x 64 64M x 64 128M x 64 1 2 2 SDRAMs 32Mb x 16 32Mb x 16 64Mb x 8 # of DRAMs 4 8 16 # of row/bank/column Address 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 13(A0~A12)/2(BA0~BA1)/10(A0~A9) 14(A0~A13)/2(BA0~BA1)/10(A0~A9) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms Rev. 0.4 / Jul. 2007 2 1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN DESCRIPTION Symbol Type Polarity Cross Point Pin Description The system clock inputs. All address and commands lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS and WE define the operation to be executed by the SDRAM. Selects which DDR2 SDRAM internal bank of four is activated. Active High Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data Input/Output pins. Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobe, associated with one data byte, sourced whit data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of th.


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