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HYMP151R72CP4-E3 Dataheets PDF



Part Number HYMP151R72CP4-E3
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 240pin Registered DDR2 SDRAM DIMMs based on 1Gb
Datasheet HYMP151R72CP4-E3 DatasheetHYMP151R72CP4-E3 Datasheet (PDF)

240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (.

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240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) • • • • • • • • Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x4/x8) 133.35 x 30.00 mm form factor RoHS compliant • • • • • • ORDERING INFORMATION Part Name HYMP112P72CP8-C4/Y5/S5/S6 HYMP125P72CP4-C4/Y5/S5/S6 HYMP151P72CP4-C4/Y5/S5/S6 HYMP112R72CP8-E3/C4 HYMP125R72CP4-E3/C4 HYMP151R72CP4-E3/C4 Density 1GB 2GB 4GB 1GB 2GB 4GB Organization 128Mx72 256Mx72 512Mx72 128Mx72 256Mx72 512Mx72 # of DRAMs 9 18 36 9 18 36 # of ranks 1 1 2 1 1 2 Parity Support O O O X X X This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Jun. 2007 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) Speed@CL3 Speed@CL4 Speed@CL5 CL-tRCD-tRP 400 3-3-3 C4 (DDR2-533) 400 533 4-4-4 Y5 (DDR2-667) 400 533 667 5-5-5 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps tCK ADDRESS TABLE Density Organization 1GB 2GB 4GB 128M x 72 256M x 72 512M x 72 Ranks 1 1 2 SDRAMs 128Mb x 8 256Mb x 4 256Mb x 4 # of DRAMs 9 18 36 # of row/bank/column Address 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms Rev. 0.2 / Jun. 2007 2 1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description Symbol CK0 Type IN Polarity Positive Edge Negative Edge Active High Pin Description Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0 IN Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CKE[1:0] IN Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 On-Die Termination signals. When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Reference voltage for SSTL18 inputs Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. S[1:0] IN Active Low ODT[1:0] RAS, CAS, WE Vref VDDQ BA[2:0] IN IN Supply Supply IN Active High Active Low - Selects which DDR2 SDRAM internal bank of Eight is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA13) During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins. A[9:0],A10/AP A[13:11] IN - DQ[63:0], CB[7:0] IN - DM[8:0] IN Active High DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. VDD,VSS Supply Positive Edge Negative Edge - DQS[17:0] I/O I/O Positive line of the differential data strobe for input .


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