HMT112U6BFR8C

240pin DDR3 SDRAM Unbuffered DIMMs DDR3 SDRAM Unbuffered DIMMs Based on 1Gb B version HMT164U6BFR6C HMT112U6BFR8C HMT112U7BFR8C HMT125U6BFR8C HMT125U7BFR8C ** Contents are subject to change without prior notice. Rev. 0.1 / Apr 2009 1 HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C Revision History Revision No. 0.01 0.02 0.1 History Initial draft for internal review Added IDD Specification Updated IDD Specification Draft Date Dec. 2008 Feb. 2009 Apr. 2009 Remark Preliminary Preliminary Rev. 0.1 / Apr 2009 2 HMT164U6BFR6C HMT112U6(7)BFR8C HMT125U6(7)BFR8C Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(1Rank of x8) 3.3 1GB, 128Mx72 ECC Module(1Rank of x8) 3.4 2GB, 256Mx64 Module(2Rank of x8) 3.5 2GB, 256Mx72 ECC Module(2Rank of x8) 4. Address Mirroring Feature 4.1 DRAM Pin Wiring for Mirroring 5. Absolute Maximum Ratings 5.1 Absolute Maximum DC Ratings 5.2 Operating Temperature Range 6. AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions 6.2 DC & AC Logic Input Levels 6.2.1 For Single-ended Signals 6.2.2 For Differential Signals 6.2.3 Differential Input Cross Point 6.3 Slew Rate Definition 6.3.1 For Ended Input Signals 6.3.2 For Differential Inpu...