Document
204pin DDR3 SDRAM SODIMM
DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb T-die
HMT112S6TFR8C HMT125S6TFR8C
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 1.2 / Jul. 2010 1
Revision History
Revision No. 0.1 1.0 1.1 1.2 History Initial Release JEDEC Update Add supported CL5 DIMM Outline Corrected Draft Date Sep.2009 Nov. 2009 Jun. 2010 Jul. 2010 Remark Preliminary Web posting Web posting Web posting
Rev. 1.2 / Jul. 2010
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Description
Hynix Unbuffered Small Outline DDR3 SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Unbuffered DDR3 SDRAM SODIMMs are intended for use as main memory when installed in systems such as mobile personal computers.
Features
• VDD=1.5V +/- 0.075V • VDDQ=1.5V +/- 0.075V • VDDSPD=3.0V to 3.6V • Functionality and operations comply with the DDR3 SDRAM datasheet • 8 internal banks • Data transfer rates: PC3-10600, PC3-8500, or PC3-6400 • Bi-directional Differential Data Strobe • 8 bit pre-fetch • Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4 • On Die Termination (ODT) supported • RoHS compliant
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number HMT112S6TFR8C-G7/H9 HMT125S6TFR8C-G7/H9 Density 1GB 2GB Organization 128Mx64 256Mx64 Component Composition 128Mx8(H5TQ1G83TFR)*8 128Mx8(H5TQ1G83TFR)*16 # of ranks 1 2
Rev. 1.2 / Jul. 2010
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Key Parameters
MT/s DDR3-1066 DDR3-1333 Grade -G7 -H9 tCK (ns) 1.875 1.5 CAS Latency (tCK) 7 9 tRCD (ns) 13.125 13.5 tRP (ns) 13.125 13.5 tRAS (ns) 37.5 36 tRC (ns) 50.625 49.5 CL-tRCD-tRP 7-7-7 9-9-9
Speed Grade
Frequency [MHz] Grade CL5 -G7 -H9 667 667 CL6 800 800 CL7 1066 1066 CL8 1066 1066 1333 1333 CL9 CL10 Remark
Address Table
1GB(1Rx8) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(2Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB
Rev. 1.2 / Jul. 2010
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Pin Descriptions
Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS WE S[1:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Description Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses On Die Termination Inputs Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Num ber 2 2 2 1 1 1 2 14 1 1 3 2 1 1 2 VREFDQ VREFCA VTT VDDSPD NC Input/Output Reference Termination Voltage SPD Power Reserved for future use 1 1 2 1 2 Total: 204 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] EVENT TEST RESET VDD VSS Description Data Input/Output Data Masks Data strobes Data strobes, negative line Temperature event pin Logic Analyzer specific test pin (No connect on SODIMM) Reset Pin Core and I/O Power Ground Num ber 64 8 8 8 1 1 1 18 52
Rev. 1.2 / Jul. .