Document
CHI LIN TECHNOLOGY CO., LTD. Doc. No.
Product Specifications
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CONETNTS
No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RECORD OF REVISION SUMMARY FEATURES GENERAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS WAVEFORM OPTICAL CHARACTERISTICS BLOCK DIAGRAM INPUT / OUTPUT TERMINALS OUTLINE DRAWING QUALITY ASSURANCE PACKAGE ITEM PAGE 3 4 4 4 4 5 6~8 9~17 18~20 21 22~23 24 25 26
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RECORD OF REVISIONS
Revision No. Revision Date Page Summary Modify the weight of general specifications from (350) to (32)
02 02 02 02
2006/2/6 2006/2/6 2006/2/6 2006/2/6
4 4 18 25
Change Top and Tst Change viewing angle Add Quality Assurance
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1. SUMMARY This technical specification applies to 3.45“ color TFT-LCD panel. The 3.45“ color TFT-LCD panel is designed for camcorder, digital camera application and other electronic products which require high quality flat panel displays.
2. FEATURES High Resolution :230,400 Dots (320 RGB x 240) . Image Reversion: Up/Down and Left/Right.
3. GENERAL SPECIFICATIONS
Parameter Screen size Display Format Active area Dot pitch Surface treatment Pixel Configuration Outline dimension Weight View Angle direction Temperature Range Operation Storage Specifications 3.45(Diagonal) 320 RGB x 240 70.08(H) x 52.56(V) 0.073(H) x 0.219(V) Anti-glare RGB-Stripe 76.9(W) x 63.9(H) x 3.3(D) (32) 6 o’clock -20~60 -30~70 mm g ℃ ℃ Unit inch Dot mm mm
4. ABSOLUTE MAXIMUM RATINGS
Item Symbol VDD,VCC Power Voltage VGH VGL VGH –VGL Vin VOUT Condition GND=0 GND=0 GND=0 GND=0 GND=0 GND=0 Min. -0.3 -0.3 -22.0 -0.3 -0.3 -0.3 Max. 7.0 32.0 0.3 +45.0 VDD+0.3 +0.7 Unit V V V V V V Remark
Input Signal Voltage Logic Output Voltage
Note : Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above
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5.
ELECTRICAL CHARACTERISTICS
5.1. Operating conditions :
Parameter
Symbol
VCC VDD VGH VGL VIL VIH IVDD
Rating
Min. Typ. Max. 3.0 3.3 3.6 3.8 5 5.5 10 30 -17 -5 0.3 0 VDD 0.7 VDD VDD TBD
Unit
V V V V V V mA
Condition
Power Voltage Low level input voltage Hight level input voltage Analog operating current
SCL, SDI,UD,LRC,IF1,IF2
fCLKIN=27MHZ,fOEH=15.7KHZ, VDDA=5V
5.2 Power Sequence
Sequence for power on/off and Signal on/off
To prevent the device from damage due to latch-up, the power ON/OFF sequence shown below must be followed. Power ON : VDD, VCC → VGL → Input Signals → VGH Power OFF : VGH → Input Signals → VGL → VDD, VCC
5.3 LED driving conditions
Parameter Symbol Min. Typ. Max. Unit LED current 20 30 mA LED voltage VLED1,VLED2 9.2 10.2 11.2 V LED Life Time (10000) Hr Note 1 : There are 2 Groups LED , each of FB = 0.6V , VLED1,2=10.2V (typ.) Note 2 : Ta = 25℃ , Note 3 : Brightess to be decreased to 50% of the initial value Remark Note 1 Note 2,3
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6. AC Characteristics
6.1. Input signal characteristics
6.1.1. CCIR601/656 Interface PARAMETER CLK period Data setup time Data hold time 6.1.2 Hardware reset timing PARAMETER RESET low pulse width Symbol TRSB Min. 10 Typ. Max. Unit μs Symbol TOSC TSU THD Min. 12 12 Typ. 37 Max. Unit ns ns ns
6.2. Output signal characteristics for Digital input signal PARAMETER Rising time Falling time Internal STH setup time Internal STH hold time Internal data setup time Internal data hold time OEH pulse width OEV pulse width CKV pulse width Hsync – DEH time Hsync – CKV time Hsync – OEV time Vsync – setup time Vsync – pulse time Vsync – STV time OEH – STV time Output settling time NTSC PAL Symbol Tr Tf TSUS THDS TSUD THDD TOEH TOEV TCKV T1 T2 T3 TSUV TSTV TVS1 TVS1 THE TOES Min. 12 12 60 40 Typ. 1248 4992 3744 4368 2496 624 1872 1 19 27 2 12 Max. 10 10 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns TH TH TH TH μs
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6.2. 24-bits parallel RGB Interface
6.2.1. AC Timing characteristics Signal
Dclk
Item
Frequency High Time Low Time
Symbol
Dclk Tch Tcl Tds Tdh TH Thp Thb Thd Thf Tv Tvp Tvb Tvd Tvf
Min
12 12 1 -
Typ
6.4 78 78 408 30 38 320 20 262.5 312.5 3 15 23 240 4.5 46.5
Max
5 -
Unit
MHZ ns ns ns ns DCLK DCLK DCLK DCLK DCLK TH TH TH TH TH
Data
Setup Time Hold Time Period Pulse Width
Hsync
Back-Porch Display Period Front-Porch Period NTSC PAL
Pulse Width Vsync Back-Porch NTSC PAL
Display Period Front-Porch NTSC PAL
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6.1.2.2
AC Timing Diagrams
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7. Waveform 7.1. Timing Controller Timing Chart 7.1.1. Clock and Data waveform
CCIR601( HS_POL="L" in Register R2)
TOSC
Data CLK DATA[23:0] Hsync Blanking data
TSU THD Cb0 Y0 Cr0 Y1 Cb2
CCIR656 Data CLK
TOSC
TSU THD
DATA[23:0]
Cb
Y
Cr
Y
Cb
Y
Cr
7.1.2 Digital / Analog RGB timing waveform 7.1.2.1 Hsync and Vsync timing
O.