A036QN02-V1

0 Record of Revision Version Revise Date Page Content 0 0.1 22/Jul/2005 16/Aug/2005 18 First draft. Add “(b) In Parallel Data Interface” figure. 0.2 8/Sep/2005 0.3 03/Nov/2005 A036QN02 V1 only support CCIR-656, serial 8bit. RGB, and TTL 8bit 6-8 Correct I/O description 9-14 Modify register setting and description Delete Note 2 of 3.5.1 18 Delete “The fist line is at 14th that will be display on panel” of 19 note. 22 Add item “Vsync to 1st active line” of 3.5.2.1 24 Add 3-wire serial communication AC timing figure. Add A036QN02 V0 support “CCIR-601, YUV” interface 3 Change panel surface treatment to “Hard Coating 3H” after 4 Dec/ ’05. Add register setting of “parallel RGB data input”. 11 16-17 Update application circuit 18-20 Correct symbol. Delete “The fist line is at 14th that will be display on panel.” 21 Correct third-item from “Hsync pulse width” to “Hsync Period” Add timing parameter “Hsync pluse width”, “Vsync period”, “Vertical active area”, “Vsync pulse width” at 3.5.2.1. 3 Data Modul AG - www.data-modul.com 1 Contents GENERAL DESCRIPTION FEATURES 3 3 1. GENERAL INFORMATION 4 2. ELECTRICAL SPECIFICATIONS 2.1 FPC PIN ASSIGNMENT 2.2 ABSOLUTE MAXIMUM RATINGS 6 6 8 3. ELECTRICAL CHARACTERISTICS 3.1 TFT- LCD TYPICAL OPERATION CONDITION 3.2 REGISTER INFORMATION 3.2.1 REGISTER SETTING 3.3 BACKLIGHT DRIVING CONDITIONS 3.4 SUGGESTED APPLICATION CIRCUIT 3.4.1 SUGGESTED APPLICATION CIRCUIT 3.4.2 APPLICATION CIRCUIT WITH USING EXTERNAL LED POWER SOURCE 3.5 AC TIM...