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UPD4217405L-A70 Dataheets PDF



Part Number UPD4217405L-A70
Manufacturers NEC
Logo NEC
Description 3.3V OPERATION 16M-BIT DYNAMIC RAM
Datasheet UPD4217405L-A70 DatasheetUPD4217405L-A70 Datasheet (PDF)

DATA SHEET µPD42S17405L, 4217405L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, EDO MOS INTEGRATED CIRCUIT Description The µPD42S17405L, 4217405L are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation. Besides, the µPD42S17405L can execute CAS before RAS self refresh. The µPD42S17405L, 4217405L are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ. Features • EDO (Hyper page mode) • 4,194,304 .

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DATA SHEET µPD42S17405L, 4217405L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, EDO MOS INTEGRATED CIRCUIT Description The µPD42S17405L, 4217405L are 4,194,304 words by 4 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation. Besides, the µPD42S17405L can execute CAS before RAS self refresh. The µPD42S17405L, 4217405L are packaged in 26-pin plastic TSOP (II) and 26-pin plastic SOJ. Features • EDO (Hyper page mode) • 4,194,304 words by 4 bits organization • Single +3.3 V ±0.3 V power supply • Fast access and cycle time Power consumption Active (MAX.) 660 mW 360 mW 324 mW Part number Access time (MAX.) 50 ns 60 ns 70 ns R/W cycle time (MIN.) 84 ns 104 ns 124 ns EDO (Hyper page mode) cycle time (MIN.) 20 ns 25 ns 30 ns µPD42S17405L-A50, 4217405L-A50 µPD42S17405L-A60, 4217405L-A60 µPD42S17405L-A70, 4217405L-A70 • µPD42S17405L can execute CAS before RAS self refresh Power consumption at standby (MAX.) 0.54 mW (CMOS level input) Part number Refresh cycle 2,048 cycles/128 ms Refresh CAS before RAS self refresh CAS before RAS refresh RAS only refresh Hidden refresh CAS before RAS refresh RAS only refresh Hidden refresh µPD42S17405L µPD4217405L 2,048 cycles/32 ms 1.8 mW (CMOS level input) The information in this document is subject to change without notice. Document No. M10068EJ6V0DS00 (6th edition) Date Published January 1997 N Printed in Japan The mark shows major revised points. © 1995 µPD42S17405L, 4217405L Ordering Information Access time (MAX.) 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 26-pin plastic SOJ (300 mil) 26-pin plastic TSOP (II) (300 mil) CAS before RAS refresh RAS only refresh Hidden refresh 26-pin plastic SOJ (300 mil) Part number Package 26-pin plastic TSOP (II) (300 mil) Refresh CAS before RAS self refresh CAS before RAS refresh RAS only refresh Hidden refresh µPD42S17405LG3-A50-7JD µPD42S17405LG3-A60-7JD µPD42S17405LG3-A70-7JD µPD42S17405LLA-A50 µPD42S17405LLA-A60 µPD42S17405LLA-A70 µPD4217405LG3-A50-7JD µPD4217405LG3-A60-7JD µPD4217405LG3-A70-7JD µPD4217405LLA-A50 µPD4217405LLA-A60 µPD4217405LLA-A70 2 µPD42S17405L, 4217405L Pin Configurations (Marking Side) 26-pin Plastic TSOP (II) (300 mil) 26-pin Plastic SOJ (300 mil) VCC I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 26 25 24 23 22 21 GND I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 26 25 24 23 22 21 GND I/O4 I/O3 CAS OE A9 µ PD42S17405LLA µ PD4217405LLA µ PD42S17405LG3-7JD µ PD4217405LG3-7JD 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 GND 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 GND A0 to A10 : Address Inputs I/O1 to I/O4: Data Inputs/Outputs RAS CAS WE OE V CC GND NC : Row Address Strobe : Column Address Strobe : Write Enable : Output Enable : Power Supply : Ground : No Connection 3 µPD42S17405L, 4217405L Block Diagram RAS CAS WE Data Output Buffer Clock Generator OE VCC GND CAS before RAS Counter Row Decoder 2,048 Memory Cell Array 2,048 × 2,048 × 4 I/O1 to I/O4 Row Address Buffer A0 to A10 Column Address Buffer X0 - X10 2,048 × 4 ×4 Sense Amplifier 2,048 Y0 - Y10 Column Decoder Data Input Buffer 4 µPD42S17405L, 4217405L Input/Output Pin Functions The µPD42S17405L, 4217405L have input pins RAS, CAS, WE, OE, A0 to A10 and input/output pins I/O1 to I/O4. Pin name RAS (Row address strobe) Input/Output Input Function RAS activates the sense amplifier by latching a row address and selecting a corresponding word line. It refreshes memory cell array of one line selected by the row address. It also selects the following function. • CAS before RAS refresh CAS activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. Address bus. Input total 22-bit of address signal, upper 11-bit and lower 11-bit in sequence (address multiplex method). Therefore, one word is selected from 4,194,304-word by 4-bit memory cell array. In actual operation, latch row address by specifying row address and activating RAS. Then, switch the address bus to column address and activate CAS. Each address is taken into the device when RAS and CAS are activated. Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH) are specified for the activation of RAS and CAS. CAS (Column address strobe) A0 to A10 (Address inputs) Input Input WE (Write enable) OE (Output enable) Input Write control signal. Write operation is executed by activating RAS, CAS and WE. Read control signal. Read operation can be executed by activating RAS, CAS and OE. If WE is activated during read operation, OE is to be ineffective in the device. Therefore, read operation cannot be executed. Input I/O1 to I/O4 (Data inputs/outputs) Input/Output 4-bit data bus. I/O1 to I/O4 are used to input/output data. 5 µPD42S17405L, 4217405L Hyper Page Mode (EDO) The hyper page mode (EDO) is a kind of page mode with enhanc.


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