Document
STMIPID02
Datasheet
Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer
VFBGA
Features
• Dual mode camera de-serializer • MIPI CSI-2 receivers
– Two-camera interface support – One 1.6 Gbps dual data lane receiver for main camera with selectable 1/2
lane operation – One 800 Mbps single data lane receiver for second camera – Each MIPI D-PHY interface has a 400 MHz DDR clock lane – MIPI D-PHY Pass through mode – Selectable 0.81 or 0.9 D-PHY revision specification • SMIA CCP2 receivers – Two-camera interface support – 650 Mbps class 2 receivers with selectable data/clock and data/strobe
operation • Support for MIPI CSI-2 and SMIA CCP2 RAW6, RAW7, RAW8 (generic),
RAW10 and RAW12 Raw Bayer format data unpacking • Support for YUV, RGB and JPEG formats • Support for SMIA 8-10, 7-10, 6-10, 10-12,8-12, 7-12, and 6-12 DPCM/PCM
decompression options • 1V8, 200 MHz,12-bit parallel output interface • HSYNC, VSYNC, and continuous PCLK output data qualification signal • Tristate-able output for dual camera systems • Error interrupt output (D-PHY and protocol) • MIPI CSI-2 short packet interrupt output • 2-wire 100/400 kHz control interface (I2C compatible slave) to configure D-PHY
timeouts and pixel data unpacking/decompression options • Integrated power on reset cell • Digital power supply: 1.7 V to 1.9 V • Integrated 1.2 V regulator for D-PHY and core logic • VFBGA 49 ball, 3 mm x 3 mm x 1 mm, 0.4 mm pitch, 0.25 mm ball package • Lead-free RoHS compliant product
Description
The STMIPID02 is a dual mode MIPI CSI-2 / SMIA CCP2 de-serializer targeted at mobile camera phone applications. Manufactured using ST 65 nm process, it integrates two MIPI CSI-2 / SMIA CCP2 receivers. The STMIPID02 can then support the main and the second cameras of a mobile camera phone.
One of the two MIPI CSI-2 receivers is a dual lane receiver allowing connection to high resolution / high frame rate cameras.
The SMIA CCP2 compatible receivers share the same input balls as the MIPI CSI-2 receivers.
STMIPID02’s 12-bit parallel output interface is capable of outputting de-serialized pixel data at rates up to 200 MHz.
DS12803 - Rev 1 - October 2018 For further information contact your local STMicroelectronics sales office.
www.st.com
STMIPID02
Pass through mode allows the STMIPID02 to be used as a standalone MIPI D-PHY physical layer device. With this device a host with a standard 8-bit, 10-bit or 12-bit parallel input interface can be connected to camera modules with either a MIPI CSI-2 or a SMIA CCP2 lowvoltage, fully differential bit-serial, low EMI interface. There is an interrupt output for every MIPI CSI-2 short packet. Power management is simplified by the presence of an integrated 1.2 V regulator to supply the MIPI D-PHY receiver and core logic. The STMIPID02 is fully configurable via an I2C compatible slave control I/F.
DS12803 - Rev 1
page 2/50
STMIPID02
Block diagram
1
Block diagram
Figure 1. Block diagram
Doubles as CCP2 data & clock/strobe
inputs
Data Lane 2 80-800Mbps DATA1P2 DATA1N2
Clock Lane 2 40-400MHz
CLKP2 CLKN2
Data Lane 1.2 80-800Mbps DATA2P1 DATA2N1
Doubles as CCP2 data & clock/strobe
inputs
Data Lane 1.1 80-800Mbps DATA1P1 DATA1N1
Clock Lane 1 40-400MHz
CLKP1 CLKN1
Slave data lane module
Data lane control interface logic
Slave clock lane module
Clock lane control interface logic
MIPI D-PHY RX
Slave data lane module
Data lane control interface logic
Slave data lane module
Data lane control interface logic
Slave clock lane module
Clock lane control interface logic
Lane merging Low level protocol Byte to pixel conversion Decompression OIF
MIPPIroCtSoIc-2olRX STMIPID02
SMIA CCP2 RX
Clock recovery & de-serializer
XSDN
1.2V voltage regulator (LDO)
Power on reset
JTAG controller
Clock manager
400kHz I2C slave
VDDOUT_LDO 1V8
ERROR INT
1V8 12-bit parallel interface @ 200MHz D[11:0]
VSYNC HSYNC PCLK (up to 200MHz)
EXTCLK 6.0MHz - 27MHz SDA SCL
DS12803 - Rev 1
page 3/50
STMIPID02
Application diagrams
2
Application diagrams
2nd camera module with MIPI CSI-2 interface or parallel interface
Main camera module with MIPI CSI-2 interface
Figure 2. MIPI CSI-2 application diagram
If Parallel Output
MIPI CSI-2 1 x 800Mbps
Data (80Mbps -> 800Mbps)
STMIPID02
DDR Clock (40MHz -> 400MHz)
MIPI CSI-2 2 x 800Mbps
Data2 (80Mbps -> 800Mbps)
Data1 (80Mbps -> 800Mbps)
DDR Clock (40MHz -> 400MHz) 100/400 kHz I2C
6-b, 7-b, 8-b, 10-b or 12-b
// pixel data
Baseband or
application processor or multi-media processor or ‘backend IC’
2nd camera module with SMIA CCP2 interface or Parallel Interface
Main camera module with SMIA CCP2 interface
Figure 3. SMIA CCP2 application diagram
If Parallel Output
SMIA CCP2 Class 2 1 x 650Mbps
Data (up to 650Mbps)
Clock / Strobe
STMIPID02
SMIA CCP2 Class 2 1 x 650Mbps
Data (up to 650Mbps)
Clock / Strobe 100/400 kHz I2C
6-b, 7-b, 8-b, 10-b or 12-b
// pixel data
Baseband or
application processor or multi-media processor or ‘backend I.