25DF161

Features Single 2.7V - 3.6V Supply Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 – Supports RapidS Operation – Supports Dual-Input Program and Dual-Output Read Very High Operating Frequencies – 100 MHz for RapidS – 85 MHz for SPI – Clock-to-Output (tV) of 5 ns Maximum Flexible, Optimized Erase Architecture for Code + Data Storage Applications – Uniform 4-Kbyte Block Erase – Uniform 32-Kbyte Block Erase – Uniform 64-Kbyte Block Erase – Full Chip Erase Individual Sector Protection with Global Protect/Unprotect Feature – 32 Sectors of 64-Kbytes Each Hardware Controlled Locking of Protected Sectors via WP Pin Sector Lockdown – Make Any Combination of 64-Kbyte Sectors Permanently Read-Only 128-Byte Programmable OTP Security Register Flexible Programming – Byte/Page Program (1 to 256 Bytes) Fast Program and Erase Times – 1.0 ms Typical Page Program (256 Bytes) Time – 50 ms Typical 4-Kbyte Block Erase Time – 250 ms Typical 32-Kbyte Block Erase Time – 400 ms Typical 64-Kbyte Block Erase Time Program and Erase Suspend/Resume Automatic Checking and Reporting of Erase/Program Failures Software Controlled Reset JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation – 5 mA Active Read Current (Typical at 20 MHz) – 5 µA Deep Power-Down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-...