3.3V 256K X 16/18 SRAM
December 2002
AS7C33256NTD16A AS7C33256NTD18A
®
9 .î 65$0 ZLWK 17'TM
Features
• Organization: 262,144 word...
Description
December 2002
AS7C33256NTD16A AS7C33256NTD18A
®
9 .î 65$0 ZLWK 17'TM
Features
Organization: 262,144 words × 16 or 18 bits NTD™1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0/5.0 ns Fast OE access time: 3.5/4.0/5.0 ns Fully synchronous operation Flow-through or pipelined mode Asynchronous output enable control
1 NTD is a trademark of Alliance Semiconductor Corporation.
Economical 100-pin TQFP package Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typical standby power Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation
Logic block diagram
Pin arrangement for TQFP (top view)
A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC NC A A
A[17:0]
18
CE0 CE1 CE2
R/W BWa BWb ADV / LD
FT LBO
ZZ
D Aredgdirsetesrs Q Burst logic
CLK
Control logic
CLK
DQ [a:b] 16/18
D Data Q Input Register
CLK
CLK CEN
18
DQ
Write delay addr. registers
CLK
18
16/18
Write Buffer
CLK
256K x 16/18 SRAM Array
16/18 16/18
16/18
CLK
Output Register
OE
16/18
OE DQ [a:b]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC NC VDDQ VSSQ
NC NC DQb DQb VSSQ VDDQ DQb DQB
FT VDD NC VSS DQb DQb VDDQ VSSQ
DQb DQb DQPb, NC
NC VSSQ VDDQ
NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2...
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