3.3V 128K X 32/36 SRAM
December 2002
AS7C33128NTD32A AS7C33128NTD36A
9 .î 65$0 ZLWK 17'TM
Features
• Organization: 131,072 word...
Description
December 2002
AS7C33128NTD32A AS7C33128NTD36A
9 .î 65$0 ZLWK 17'TM
Features
Organization: 131,072 words × 32 or 36 bits NTD™1 architecture for efficient bus operation
Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0/5.0 ns Fast OE access time: 3.5/4.0/5.0 ns Fully synchronous operation Flow-through or pipelined mode Asynchronous output enable control
1. NTD™ is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
Economical 100-pin TQFP package Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typical standby power Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation
Pin arrangement for TQFP (top view)
A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC NC A A
A[16:0]
17
CE0 CE1 CE2
R/W BWa BWb BWc BWd ADV / LD
FT LBO
ZZ
DQ [a:d]
32/36
D AredgdirsetessrQ Burst logic
CLK
Control logic
CLK
D
Data Input
Q
Register
CLK
CLK
CEN
17 17
17
DQ
Write delay addr. registers
CLK
17
Write Data Registers
CLK
32/36
128K x 32/36 SRAM Array
32/36
32/36
32/36
CLK
Output OE Register
32/36 OE DQ [a:d]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPc, NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD VDD VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd
DQPd, NC
1 2 3 4 5...
Similar Datasheet