AS6WA25616

September 2001 AS6WA25616 Š 3.0V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable Features AS6WA25616 Intelliwatt™ active power circuitry Industrial and commercial temperature ranges available Organization: 262,144 words × 16 bits 3.0V to 3.6V at 55 ns Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns Low power consumption: STANDBY - 72 µW max at 3.6V Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 Row Decoder I/O buffer 256K × 16 Array (4,194,304) VCC VSS Control circuit WE Column decoder A5 A9 A10 A11 A14 A15 A16 A17 UB OE LB CS 1.5V data retention Equal access and cycle times Easy memory expansion with CS, OE inputs Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP 2 ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA Pin arrangement (top view) 44-pin 400-mil TSOP 2 A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 I/VVOCS5CS I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VVI/SCOSC12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 48-CSP Ball-Grid-Array Package 123456 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC Selection guide Product AS6WA25616 Min (V) 3.0 V...