Document
dsPIC33EVXXXGM00X/10X FAMILY
16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features
Operating Conditions
• 4.5V to 5.5V, -40°C to +85°C, DC to 70 MIPS • 4.5V to 5.5V, -40°C to +125°C, DC to 60 MIPS • 4.5V to 5.5V, -40°C to +150°C, DC to 40 MIPS
Core: 16-Bit dsPIC33E CPU
• Code-Efficient (C and Assembly) Architecture • 16-Bit Wide Data Path • Two 40-Bit Wide Accumulators • Single-Cycle (MAC/MPY) with Dual Data Fetch • Single-Cycle, Mixed-Sign MUL plus Hardware
Divide • 32-Bit Multiply Support • Intermediate Security for Memory:
- Provides a Boot Flash Segment in addition to the existing General Flash Segment
• Error Code Correction (ECC) for Flash • Added Two Alternate Register Sets for Fast
Context Switching
Clock Management
• Internal, 15% Low-Power RC (LPRC) – 32 kHz • Internal, 1% Fast RC (FRC) – 7.37 MHz • Internal, 10% Backup RC (BFRC) – 7.37 MHz • Programmable PLLs and Oscillator Clock Sources • Fail-Safe Clock Monitor (FSCM) • Additional FSCM Source (BFRC), Intended to
Provide a Clock Fail Switch Source for the System Clock • Independent Watchdog Timer (WDT) • System Windowed Watchdog Timer (DMT) • Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle and Doze)
• Power Consumption Minimized Executing NOP String
• Integrated Power-on Reset (POR) and Brown-out Reset (BOR)
• 0.5 mA/MHz Dynamic Current (typical) • 50 µA at +25°C IPD Current (typical)
PWM
• Up to Six Pulse-Width Modulation (PWM) Outputs (three generators)
• Primary Master Time Base Inputs allow Time Base Synchronization from Internal/External Sources
• Dead Time for Rising and Falling Edges • 7.14 ns PWM Resolution • PWM Support for:
- DC/DC, AC/DC, inverters, Power Factor Correction (PFC) and lighting
- Brushless Direct Current (BLDC), Permanent Magnet Synchronous Motor (PMSM), AC Induction Motor (ACIM), Switched Reluctance Motor (SRM)
- Programmable Fault inputs - Flexible trigger configurations for
Analog-to-Digital conversion - Supports PWM lock, PWM output chopping
and dynamic phase shifting
Advanced Analog Features
• ADC module: - Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H - Up to 36 analog inputs
• Flexible and Independent ADC Trigger Sources • Up to Four Op Amp/Comparators with Direct
Connection to the ADC module: - Additional dedicated comparator and
7-bit Digital-to-Analog Converter (DAC) - Two comparator voltage reference outputs - Programmable references with 128 voltage
points - Programmable blanking and filtering • Charge Time Measurement Unit (CTMU): - Supports mTouch™ capacitive touch sensing - Provides high-resolution time
measurement (1 ns) - On-chip temperature measurement - Temperature sensor diode - Nine sources of edge input triggers (CTED1,
CTED2, OCPWM, TMR1, SYSCLK, OSCLK, FRC, BFRC and LPRC)
2013-2014 Microchip Technology Inc.
DS70005144C-page 1
dsPIC33EVXXXGM00X/10X FAMILY
Timers/Output Compare/Input Capture
• Nine General Purpose Timers: - Five 16-bit and up to two 32-bit timers/counters; Timer3 can provide ADC trigger
• Four Output Capture modules Configurable as Timers/Counters
• Four Input Capture modules
Communication Interfaces
• Two Enhanced Addressable Universal Asynchronous Receiver/Transmitter (UART) modules (6.25 Mbps): - With support for LIN/J2602 bus support and IrDA® - High and low speed (SCI)
• Two SPI modules (15 Mbps): - 25 Mbps data rate without using PPS
• One I2C™ module (up to 1 Mbaud) with SMBus Support
• Two SENT J2716 (Single-Edge Nibble Transmission-Transmit/Receive) module for Automotive Applications
• One CAN module: - 32 buffers, 16 filters and three masks
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority Arbitration
• UART, Serial Peripheral Interface (SPI), ADC, Input Capture, Output Compare and Controller Area Network (CAN)
Input/Output
• GPI/O Registers to Support Selectable Slew Rate I/O
• Peripheral Pin Select (PPS) to allow Function Remap
• Sink/Source: 8 mA or 12 mA, Pin-Specific for Standard VOH/VOL
• Selectable Open-Drain, Pull-ups and Pull-Downs • Change Notice Interrupts on All I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1: -40°C to +125°C) Completed
• AEC-Q100 REVG (Grade 0: -40°C to +150°C) Planned
• Class B Safety Library, IEC 60730
Class B Fault Handling Support
• Backup FRC • Windowed WDT uses LPRC • Windowed Deadman Timer (DMT) uses System
Clock (System Windowed Watchdog Timer) • H/W Clock Monitor Circuit • Oscillator Frequency Monitoring through CTMU
(OSCI, SYSCLK, FRC, BFRC, LPRC) • Dedicated PWM Fault Pin • Lockable Clock Configuration
Debugger Development Support
• In-Circuit and In-Application Programming • Three Complex and Five Simple Breakpoints • Trace and Run-Time Watch
DS70005144C-page 2
2013-2014 Microchip Technology Inc.
Program Memory Bytes SRAM Bytes CAN
DMA Channels 16-Bit Timers (T1)
32-Bit Timers Input Capture Output Compare
PWM UART
SPI I2C™ SENT 10/12-Bit ADC ADC Inputs Op Amp/Comparator.