Document
DM74S10 Triple 3-Input NAND Gate
August 1986 Revised April 2000
DM74S10 Triple 3-Input NAND Gate
General Description
This device contains three independent gates each of which performs the logic NAND function.
Ordering Code:
Order Number Package Number
Package Description
DM74S10
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Y = ABC
Inputs AB XX XL LX HH
H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level
C L X X H
Output Y H H H L
© 2000 Fairchild Semiconductor Corporation DS006446
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DM74S10
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range
7V 5.5V 0°C to +70°C −65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol
VCC VIH VIL IOH IOL TA
Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature
Min 4.75
2
0
Nom 5
Max 5.25
0.8 −1 20 70
Units V V V mA mA °C
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level Output Voltage
VCC = Min, IOH = Max VIL = Max
2.7
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min
II
Input Current @ Max Input Voltage
VCC = Max, VI = 5.5V
IIH HIGH Level Input Current
VCC = Max, VI = 2.7V
IIL LOW Level Input Current
VCC = Max, VI = 0.5V
IOS Short Circuit Output Current
VCC = Max (Note 3)
−40
ICCH
Supply Current with Outputs HIGH
VCC = Max
ICCL
Supply Current with Outputs LOW
VCC = Max
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ (Note 2)
3.4
7.5 15
Max −1.2
0.5 1 50 −2 −100 12 27
Units
V
V
V
mA µA mA mA mA mA
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
tPLH Propagation Delay Time LOW-to-HIGH Level Output
tPHL Propagation Delay Time HIGH-to-LOW Level Output
RL = 280Ω
CL = 15 pF
CL = 50 pF
Min Max Min Max
2 4.5 2
7
2528
Units ns ns
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DM74S10 Triple 3-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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