GTLP16616

GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock June 1997 Revised October 1998 GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock General Description The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. Features s Bidirectional interface between GTLP and TTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down/off high impedance for live insertion s External VREF pin for receiver threshold s CMOS technology for low power dissipation s 5 V tolerant inputs and outputs on the A-Port s B...