GTLP17T616

GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock January 2000 Revised February 2000 GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock General Description The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. Features s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold adjustability s BiCMOS technology for low power dissipation s Bushold data inputs...