GTLP36T612

GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver September 2001 Revised July 2002 GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver General Description The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V. Features s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s Partitioned as two 18-Bit transceivers with individual latch timing and output control s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance ov...