Document
25Q16BSIG
FEATURES
◆ 16M-bit Serial Flash -2048K-byte -256 bytes per programmable page
◆ Standard, Dual, Quad SPI -Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# -Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# -Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ High Speed Clock Frequency -120MHz for fast read with 30PF load -Dual I/O Data transfer up to 180Mbits/s -Quad I/O Data transfer up to 360Mbits/s
◆ Program/Erase Speed -Page Program time: 0.7ms typical -Sector Erase time: 100ms typical -Block Erase time: 0.3/0.4/0.8s typical -Chip Erase time: 16s typical
◆ Flexible Architecture -Sector of 4K-byte -Block of 32/64/128K-byte
◆ Low Power Consumption -20mA maximum active current -5uA maximum power down current
◆ Software/Hardware Write Protection -Write protect all/portion of memory via software -Enable/Disable protection with WP# Pin -Top or Bottom, Sector or Block selection
◆ Minimum 100,000 Program/Erase Cycles Note: 1.Please contact Gigadevice for details.
◆ Advanced security Features(1) -16-Bit Customer ID -Security Architecture
◆ Single Power Supply Voltage -Full voltage range:2.7~3.6V
GENERAL DESCRIPTION
The GD25Q16 (16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of 360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO WP#
27 Top View
36
VSS
45 8–LEAD SOP/DIP
VCC HOLD# SCLK SI
1
Uniform Sector Dual and Quad Serial Flash
PIN DESCRIPTION
Pin Name
I/O
CS# I
SO (IO1)
I/O
WP# (IO2)
I/O
VSS
SI (IO0)
I/O
SCLK
I
HOLD# (IO3)
I/O
VCC
Description Chip Select Input Data Output (Data Input Output 1) Write Protect Input (Data Input Output 2) Ground Data Input (Data Input Output 0) Serial Clock Input Hold Input (Data Input Output 3) Power Supply
BLOCK DIAGRAM
WP#(IO2)
Write Control Logic
HOLD#(IO3) SCLK CS#
SI(IO0) SO(IO1)
SPI Command & Control Logic
Write Protect Logic and Row Decode
Status Register
High Voltage Generators
Flash Memory
Page Address Latch/Counter
Column Decode And 256-Byte Page Buffer
Byte Address Latch/Counter
GD25Q16
2
Uniform Sector Dual and Quad Serial Flash
GD25Q16
MEMORY ORGANIZATION
Each device has
Each block has
2M 128/64/32K
8K 512/256/128
512 32/16/8
16/32/64
-
Each sector has 4K 16 -
Each page has 256 -
bytes pages sectors blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25Q16 64K Bytes Block Sector Architecture
Block
Sector
31 30 …… ……
511 …… 496 495 …… 480 …… …… …… …… …… ……
47 2 ……
32 31 1 …… 16 15 0 …… 0
Address range
1FF000H ……
1F0000H 1EF000H
…… 1E0000H
…… …… …… …… …… …… 02F000H …… 020000H 01F000H …… 010000H 00F000H …… 000000H
1FFFFFH ……
1F0FFFH 1EFFFFH
…… 1E0FFFH
…… …… …… …… …… …… 02FFFFH …… 020FFFH 01FFFFH …… 010FFFH 00FFFFH …… 000FFFH
3
Uniform Sector Dual and Quad Serial Flash
GD25Q16
DEVICE OPERATION SPI Mode
Standard SPI The GD25Q16 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI The GD25Q16 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI The GD25Q16 supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad
I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low.
Figure1. Hold Condition
CS# SCLK HOLD#
HOLD
H.