Document
EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
General Description
The EM25LV010 is a 1 M bits Flash memory organized as 128K x 8 bits and uses a single voltage of 2.7-3.6V for Program and Erase. It features a typical 2ms Page-Program time and a typical 40ms Block-Erase time. The device uses status register to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes. The device offers typical 100,000 cycles endurance and a greater than 10 years data retention. The EM25LV010 conforms to SPI Bus compatible Serial Interface. It consisted of four pins (serial clock, chip select, serial data in, and serial data out) that support high-speed serial data transfers of up to 33MHz. The Hold pin, Write Protect pin, and Programmable Write Protect features provide flexible control. The EM25LV010 is offered in 8-lead SO package and known good die (KGD). For KGD, please contact ELAN Microelectronics or its representatives for detailed information (see Appendix at the bottom of this specification for Ordering Information).
The EM25LV010 devices are suitable for applications that require memories with convenient and economical updating of program, data or configurations, e.g., graphic cards, hard disk drives, networking cards, digital camera printer, LCD monitors, cordless Phones, etc.
Features
Single Power Supply • Full voltage range from 2.7 to 3.6
volts for both read and write operations • Regulated voltage range: 3.0 to 3.6
volts for both read and write operations
Small block Erase Capability Block: Uniform 32K bytes
Clock Rate • 33MHz (Maximum)
Power Consumption • Active Current: 4mA (Typical) • Power-down Mode Standby
current: 1µA (Typical)
Page Program Features • Up to 256 Bytes in 2ms (Typical)
Erase Features • Block-Erase Time: 40ms (Typical) • Chip-Erase Time: 40ms (Typical)
Automatic Write Timing • Internal VPP Generation SPI Bus Compatible Serial Interface
High Reliability: • Endurance cycles: 100K (Typical) • Data retention: 10 years
Package Option • 8-lead-SO (150 mil)
This specification is subject to change without further notice. (11.08.2004 V1.0)
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Pin Assignments
EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
S# Q W# VSS
18 2 SO8 7 3 Top View 6 45
VCC
HOLD# C D
Figure 0: Pin Assignments
Pin Description
Pin Name
C D Q S# W# Hold# VDD VSS
Function
Serial Clock 1 Serial Data Input 2 Serial Data Output 3 Chip Select 4 Write Protect 5 Hold 6
Supply Voltage
Ground
Table 1: Pin Description
1 Serial Clock (C):
This input pin provides the timing for serial input and output operations. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2 Serial Data Input (D):
This input pin provides a means for instructions, addresses, and data to be serially written to the device. Data is latched on the rising edge of Serial Clock (C).
3 Serial Data Output (Q):
This output pin provides a means for data and status to be serially read from the device. Data is shift out on the falling edge of Serial Clock (C).
This specification is subject to change without further notice. (11.08.2004 V1.0)
Page 2 of 30
EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
4 Chip Select (S#):
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance state. Unless an internal Program, Erase, or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S#) Low enables the device, and places it in the active power mode. After Power-up, a falling edge on Chip Select (S#) is required prior to the start of any instruction.
5 Write Protect (W#):
This input pin can be used to prevent the Status Register from being written and active low. When used in conjunction with the Status Register’s Block Protect (BP1 and BP1) bits and Status Register Protect (SRWD) bits, a portion of or the entire memory array can be hardware protected.
6 Hold (HOLD#):
This input pin is used to pause any serial communications with the device without the need to deselect the device. When HOLD# is brought low, the Serial Data Output (Q) is at high impedance state, and Serial Data Input (D) & Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected with Chip Select (S#) driven Low.
SPI Modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
CPOL=0, CPHA=0 CPOL=1, CPHA=1
Under these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master i.