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IDT74FCT573A Dataheets PDF



Part Number IDT74FCT573A
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description FAST CMOS OCTAL TRANSPARENT LATCHES
Datasheet IDT74FCT573A DatasheetIDT74FCT573A Datasheet (PDF)

® Integrated Device Technology, Inc. FAST CMOS OCTAL TRANSPARENT LATCHES IDT54/74FCT373/A/C IDT54/74FCT533/A/C IDT54/74FCT573/A/C FEATURES • IDT54/74FCT373/533/573 equivalent to FAST™ speed and drive • IDT54/74FCT373A/533A/573A up to 30% faster than FAST • Equivalent to FAST output drive over full temperature and voltage supply extremes • IOL = 48mA (commercial) and 32mA (military) • CMOS power levels (1mW typ. static) • Octal transparent latch with 3-state output control • JEDEC standard pin.

  IDT74FCT573A   IDT74FCT573A


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® Integrated Device Technology, Inc. FAST CMOS OCTAL TRANSPARENT LATCHES IDT54/74FCT373/A/C IDT54/74FCT533/A/C IDT54/74FCT573/A/C FEATURES • IDT54/74FCT373/533/573 equivalent to FAST™ speed and drive • IDT54/74FCT373A/533A/573A up to 30% faster than FAST • Equivalent to FAST output drive over full temperature and voltage supply extremes • IOL = 48mA (commercial) and 32mA (military) • CMOS power levels (1mW typ. static) • Octal transparent latch with 3-state output control • JEDEC standard pinout for DIP and LCC • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B FUNCTIONAL BLOCK DIAGRAMS IDT54/74FCT373 AND IDT54/74FCT573 D0 D1 D2 D3 DESCRIPTION The IDT54/74FCT373/A/C, IDT54/74FCT533/A/C and IDT54/74FCT573/A/C are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high-impedance state. D4 D5 D6 D7 D O G D O G D O G D O G D O G D O G D O G D O G LE OE IDT54/74FCT533 D0 O0 D1 O1 D2 O2 D3 O3 D4 O4 D5 O5 D6 O6 O7 2602 cnv* 01 D7 D O G D O G D O G D O G D O G D O G D O G D O G LE OE O0 O1 O2 O3 O4 O5 O6 O7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1992 Integrated Device Technology, Inc. 7.12 2602 cnv* 02 MAY 1992 DSC-4624/2 1 IDT54/74FCT373/533/573/A/C FAST CMOS OCTAL TRANSPARENT LATCHES PIN CONFIGURATIONS IDT54/74FCT373 OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 20 2 19 3 18 4 P20-1 17 5 D20-1 16 6 SO20-2 15 & 7 E20-1 14 8 13 9 12 10 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE DIP/SOIC/CERPACK TOP VIEW IDT54/74FCT573 OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 20 2 19 3 18 4 P20-1 17 5 D20-1 16 6 SO20-2 15 7 & E20-1 14 8 13 9 12 10 11 VCC O0 O1 O2 O3 O4 O5 O6 O7 LE DIP/SOIC/CERPACK TOP VIEW IDT54/74FCT533 OE O0 D0 D1 O1 O2 D2 D3 O3 GND 1 20 2 19 3 18 4 P20-1 17 5 D20-1 16 6 SO20-2 15 7 & E20-1 14 8 13 9 12 10 11 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE DIP/SOIC/CERPACK TOP VIEW MILITARY AND COMMERCIAL TEMPERATURE RANGES D0 O0 OE VCC O7 INDEX 3 2 20 19 D1 4 1 18 D7 O1 5 17 D6 O2 6 L20-2 16 O6 D2 7 15 O5 D3 8 14 D5 9 10 11 12 13 O3 GND LE O4 D4 LCC TOP VIEW D1 D0 OE VCC O0 INDEX 3 2 20 19 D2 4 1 18 O1 D3 5 17 O2 D4 6 L20-2 16 O3 D5 7 15 O4 D6 8 14 O5 9 10 11 12 13 D7 GND LE O7 O6 LCC TOP VIEW D0 O0 OE VCC O7 INDEX 3 2 20 19 D1 4 1 18 D7 O1 5 17 D6 O2 6 L20-2 16 O6 D2 7 15 O5 D3 8 14 D5 9 10 11 12 13 O3 GND LE O4 D4 7.12 LCC TOP VIEW 2602 cnv* 03–08 2 IDT54/74FCT373/533/573/A/C FAST CMOS OCTAL TRANSPARENT LATCHES FUNCTION TABLE (FCT533)(1) Inputs DN LE HH LH XX NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance OE L L H MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE (FCT373 and FCT573)(1) Outputs ON L H Z 2602 tbl 05 Inputs DN LE HH LH XX NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance Outputs OE ON LH LL HZ 2602 tbl 06 PIN DESCRIPTION Pin Names DN LE OE ON ON Data Inputs Description Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Complementary 3-State Outputs 2602 tbl 07 ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation Commercial –0.5 to +7.0 –0.5 to VCC 0 to +70 –55 to +125 –55 to +125 0.5 Military Unit –0.5 to +7.0 V –0.5 to VCC V –55 to +125 °C –65 to +135 °C –65 to +150 °C 0.5 W IOUT DC Output 120 120 mA Current NOTES: 2602 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 2602 tbl 02 1. This parameter is measured at characterization but not tested. 7.12 3 IDT54/74FCT373/533/573/A/C FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRI.


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