Document
Integrated Device Technology, Inc.
FAST CMOS OCTAL TRANSPARENT LATCHES
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT IDT54/74FCT533T/AT/CT
IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FEATURES:
– Reduced system switching noise
• Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages
• Features for FCT373T/FCT533T/FCT573T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) – Power off disable outputs permit “live insertion”
• Features for FCT2373T/FCT2573T: – Std., A and C speed grades – Resistor output (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.)
DESCRIPTION:
The FCT373T/FCT2373T, FCT533T and FCT573T/ FCT2573T are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high- impedance state. The FCT2373T and FCT2573T have balanced drive out-
puts with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall timesreducing the need for external series terminating resistors. The FCT2xxxT parts are plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T
D0 D1 D2 D3 D4 D5 D6 D7
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
LE
OE
O0 O1 O2 O3
FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T
D0 D1 D2 D3 D4
O4 D5
O5 D6
O6 D7
O7
2564 cnv* 01
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2564 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
©1995 Integrated Device Technology, Inc.
6.12
DSC-4216/6
1
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT373/2373T
OE O0 D0 D1 O1 O2 D2 D3
O3 GND
1 20
2 19
3 18 P20-1
4 D20-1 17
5 SO20-2 16
6 SO20-7 15
7
SO20-8 &
14
8 E20-1 13
9 12
10 11
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
2564 cnv* 03
D0 O0 OE VCC O7
INDEX
3 2 20 19
D1 4
1 18 D7
O1 5
17 D6
O2
6
L20-2
16 O6
D2 7
15 O5
D3 8
14 D5
9 10 11 12 13
O3 GND
LE O4 D4
LCC TOP VIEW
2564 cnv* 04
IDT54/74FCT573/2573T
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
1 20
2 19
3 18 P20-1
4 D20-1 17 5 SO20-2 16 6 SO20-7 15
SO20-8 7 & 14 8 E20-1 13 9 12
10 11
VCC
O0 O1 O2 O3 O4 O5 O6 O7 LE
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
2564 cnv* 05
D1 D0 OE VCC O0
INDEX
3 2 20 19
D2 4
1 18 O1
D3 5
17 O2
D4 6
L20-2
16 O3
D5 7
15 O4
D6 8
14 O5
9 10 11 12 13
D7 GND
LE O7 O6
LCC TOP VIEW
2564 cnv* 06
IDT54/74FCT533
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
1 20
2 19
3 18
4 P20-1 17
5 D20-1 16
6 SO20-2 15
7
& E20-1
14
8 13
9 12
10 11
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
DIP/SOIC/CERPACK TOP VIEW
2564 cnv* 07
D0 O0 OE VCC O7
INDEX
3 2 20 19
D1 4
1 18 D7
O1 5
17 D6
O2 6
L20-2
16 O6
D2 7
15 O5
D3 8
14 D5
9 10 11 12 13
O3 GND
LE O4 D4
LCC TOP VIEW
2564 cnv* 08
6.12 2
IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (533)(1)
Inputs DN LE
HH
LH
XX
NOTE: 1. H = HIGH Voltage Level
L = LOW Voltage Level X = Don’t Care Z = High Impedance
OE
L L H
FUNCTION TABLE (373 and 573)(1)
Outputs
ON
L H Z
2564 tbl 01
Inputs DN LE
HH
LH
XX
NOTE: 1. H = HIGH Voltage Level
L = LOW Voltage Level X = Don’t Care Z = High Impedance
OE
L L H
Outputs ON H L Z
2564 tbl 02
DEFINITION OF FUNCTIONAL TERMS
Pin Names DN
LE
OE
Data Inputs
Description
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
ON 3-State Outputs
ON Complementary 3-State Outputs
2564 tbll 03
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage with Respect to GND
VTERM(3) Terminal Voltage with Respect to GND
TA Operating Temperature
TBIAS
Temperature Under Bias
TSTG
Storage Temperature
PT Power Dissipation
Commercial –0.5 to +7.0
–0.5 to VCC +0.5 0 to +70
–55 to +125
–55 to +125
0.5
Military –0.5 to +7.0
–0.5 to VCC +0.5 –55 to +125
–65 to +135
–65 to +150
0.5
Unit V
V
°C °C °C W
IOUT
DC Output Current
–60 to +120 –60 to +120 mA
NOTES:
2564 lnk 04
1. Stresses greate.