R5F10E8CALA

Preliminary Datasheet Specifications in this document are tentative and subject to change. RL78/G1A R01DS0151EJ0001 RENESAS MCU Rev.0.01 2011.12.26 Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz 1. OUTLINE 1.1 Features Ultra-Low Power Technology 1.6 V to 3.6 V operation from a single supply Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA Halt (RTC + LVD): 0.57 µA Snooze: T.B.D. Operating: 66 µA/MHz 16-bit RL78 CPU Core Delivers 41 DMIPS at maximum operating frequency of 32 MHz Instruction Execution: 86% of instructions can be executed in 1 to 2 clock cycles CISC Architecture (Harvard) with 3-stage pipeline Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle MAC: 16 x 16 to 32-bit result in 2 clock cycles 16-bit barrel shifter for shift & rotate in 1 clock cycle 1-wire on-chip debug function Code Flash Memory Density: 16 KB to 64 KB Block size: 1 KB On-chip single voltage flash memory with protection from block erase/writing Self-programming with secure boot swap function and flash shield window function Data Flash Memory Data Flash with background operation Data flash size: 4 KB Erase Cycles: 1 Million (typ.) Erase/programming voltage: 1.8 V to 3.6 V RAM 2 KB to 4 KB size options Supports operands or instructions Back-up retention in all modes High-speed On-chip O...