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CXD3422GA Dataheets PDF



Part Number CXD3422GA
Manufacturers Sony
Logo Sony
Description Timing Generator and Signal Processor
Datasheet CXD3422GA DatasheetCXD3422GA Datasheet (PDF)

CXD3422GA Timing Generator and Signal Processor for Frame Readout CCD Image Sensor Description The CXD3422GA is a timing generator and CCD signal processor IC for the ICX284, ICX432/434 CCD image sensor. 96 pin LFLGA (Plastic) Features • Timing generator functions • Horizontal drive frequency 18 to 24.3MHz (Base oscillation frequency 36 to 48.6MHz) • Supports frame readout/draft (sextuple speed)/ AF (Auto focus drive) (ICX432 mode) • Supports frame readout/draft (quadruple speed)/ AF (Auto fo.

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CXD3422GA Timing Generator and Signal Processor for Frame Readout CCD Image Sensor Description The CXD3422GA is a timing generator and CCD signal processor IC for the ICX284, ICX432/434 CCD image sensor. 96 pin LFLGA (Plastic) Features • Timing generator functions • Horizontal drive frequency 18 to 24.3MHz (Base oscillation frequency 36 to 48.6MHz) • Supports frame readout/draft (sextuple speed)/ AF (Auto focus drive) (ICX432 mode) • Supports frame readout/draft (quadruple speed)/ AF (Auto focus drive) (ICX434 mode) • High-speed/low-speed shutter function • Horizontal and vertical drivers for CCD image sensor • CCD signal processor functions • Correlated double sampling • Programmable gain amplifier (PGA) allows gain adjustment over a wide range (–6 to +42dB) • 10-bit A/D converter • Chip Scale Package (CSP): CSP allows vast reduction in the CCD camera block footprint Applications Digital still cameras Applicable CCD Image Sensors ICX284 (Type 1/2.7, 2020K pixels) ICX432 (Type 1/2.7, 3240K pixels) ICX434 (Type 1/3.2, 2020K pixels) Absolute Maximum Ratings • Supply voltage VDDa, VDDb, VDDc, VDDd VSS – 0.3 to +7.0 V VDDe, VDDf, VDDg VSS – 0.3 to +4.0 V VL –10.0 to VSS V VH VL – 0.3 to +26.0 V • Input voltage (analog) VIN VSS – 0.3 to VDD + 0.3 V • Input voltage (digital) VI VSS – 0.3 to VDD + 0.3 V • Output voltage VO1 VSS – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V VO3 VL – 0.3 to VH + 0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +125 °C Recommended Operating Conditions • Supply voltage VDDa, VDDb, VDDc, VDDd, VDDe, VDDf, VDDg 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75 V V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E02125-PS Block Diagram CXD3422GA NC NC C3 C2 C1 AVDD3 AVDD4 AVSS3 AVSS4 AVSS5 SCK2 SSI2 SEN2 TEST3 TEST4 TEST5 DVDD1 DVSS3 DVDD2 DVSS1 DVSS2 A1 A2 C7 D8 D7 B8 B6 B9 A6 C5 A3 A4 B4 A5 C4 B5 E2 F2 F3 E3 F1 C4 C8 AVDD5 A9 AVSS6 A8 C7 B7 C8 A7 C9 C6 CCDIN C9 AVDD1 E9 AVDD2 E8 AVSS1 D9 AVSS2 E7 XSHPI F9 XSHDI F8 PBLKI F7 XSHP G9 XSHD G8 PBLK G7 VDD4 H8 VDD2 K7 RG K8 VSS2 K9 VDD3 H9 H1 J8 H2 J9 VSS3 J7 ID/EXP N9 WEN/FLD M9 VH L5 VM M3 VL M6 DAC Serial Port Register CDS PGA ADC Latch Preblanking Dummy Pixel Auto Zero Black Level Auto Zero Pulse Generator V Driver Latch 1/2 Selector Serial Port Register Selector SSG B3 D0 (LSB) B2 D1 B1 D2 C3 D3 C2 D4 C1 D5 D3 D6 D2 D7 D1 D8 E1 D9 (MSB) ADCLKI G1 CLPOBI G2 CLPDMI G3 ADCLK H1 CLPOB H2 CLPDM H3 J3 VSS4 OSCI L1 OSCO K1 CKI J1 J2 CKO K2 MCKO N8 SNCSL L2 SSI1 M1 SCK1 N1 SEN1 L8 SSGSL H7 L3 M8 L4 M5 N5 M4 L6 N6 N4 N7 M7 N2 M2 L9 K3 L7 N3 TEST1 TEST2 RST V4/V2 V5B/V3B V1/NC V2/NC V3A/V1A V3B/V1B V5A/V3A V6/V4 SUB HD VD VDD1 VDD5 VSS1 VSS5 –2– Pin Configuration (Top View) CXD3422GA A NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 B D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 C D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D D8 D7 D6 C1 C2 AVSS1 E D9 DVDD1 DVSS1 AVSS2 AVDD2 AVDD1 F DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI G ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP H ADCLK CLPOB CLPDM TEST1 VDD4 VDD3 J CKI CKO VSS4 VSS3 H1 H2 K OSCO MCKO VDD5 VDD2 RG VSS2 L OSCI SSI1 TEST2 V4 (V2) VH V3A (V1A) VSS1 SSGSL VDD1 M SCK1 VD VM V2 (NC) V5B (V3B) VL SUB RST WEN/FLD N SEN1 HD VSS5 V5A (V3A) V1 (NC) V3B (V1B) V6 (V4) SNCSL ID/EXP 1 2345 678 9 Note) The symbol in parenthesis is for ICX434 mode. –3– CXD3422GA Pin Description Pin No. Symbol A1 NC A2 NC A3 SCK2 A4 SSI2 A5 TEST3 A6 AVSS4 A7 C8 A8 AVSS6 A9 AVDD5 B1 D2 B2 D1 B3 D0 B4 SEN2 B5 TEST5 B6 AVDD4 B7 C7 B8 AVDD3 B9 AVSS3 C1 D5 C2 D4 C3 D3 C4 TEST4 C5 AVSS5 C6 C9 C7 C3 C8 C4 C9 CCDIN D1 D8 D2 D7 D3 D6 D7 C1 D8 C2 D9 AVSS1 E1 D9 E2 DVDD1 E3 DVSS1 E7 AVSS2 I/O Description — No connected. (Open) — No connected. (Open) I CCD signal processor block serial interface clock input. (Schmitt trigger) I CCD signal processor block serial interface data input. (Schmitt trigger) I CCD signal processor block test input 3. Connect to DVSS. — CCD signal processor block analog GND. — Capacitor connection. — CCD signal processor block analog GND. — CCD signal processor block analog power supply. O ADC output. O ADC output. O ADC output (LSB). I CCD signal processor block serial interface enable input. (Schmitt trigger) I CCD signal processor block test input 5. Connect to DVDD. — CCD signal processor block analog power supply. — Capacitor connection. — CCD signal processor block analog power supply. — CCD signal processor block analog GND. O .


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