Analog-to-Digital Converter. AD9255 Datasheet

AD9255 Converter. Datasheet pdf. Equivalent

AD9255 Datasheet
Recommendation AD9255 Datasheet
Part AD9255
Description 1.8 V Analog-to-Digital Converter
Feature AD9255; Data Sheet 14-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter AD9255 FEATURES SN.
Manufacture Analog Devices
Datasheet
Download AD9255 Datasheet




Analog Devices AD9255
Data Sheet
14-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9255
FEATURES
SNR = 78.3 dBFS at 70 MHz and 125 MSPS
SFDR = 93 dBc at 70 MHz and 125 MSPS
Low power: 371 mW at 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.4 dBm/Hz small signal input noise with 200 Ω input
impedance at 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and
TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5. Pin compatibility with the AD9265, allowing a simple
migration up to 16 bits.
FUNCTIONAL BLOCK DIAGRAM
SENSE RBIAS PDWN AGND AVDD (1.8V)
LVDS LVDS_RS
VREF
VCM
VIN+
VIN–
DITHER
CLK+
CLK–
SYNC
REFERENCE
AD9255
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC
14-BIT
14
CORE
OUTPUT
STAGING 14
CMOS OR
LVDS
(DDR)
SERIAL PORT
SVDD SCLK/ SDIO/ CSB
DFS DCS
Figure 1.
DRVDD (1.8V)
D13 TO D0
OR
OEB
DCO
Rev. C
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Analog Devices AD9255
AD9255
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
ADC DC Specifications................................................................. 4
ADC AC Specifications ................................................................. 5
Digital Specifications ................................................................... 6
Switching Specifications ................................................................ 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 23
Theory of Operation ...................................................................... 25
ADC Architecture ...................................................................... 25
Analog Input Considerations.................................................... 25
Data Sheet
Voltage Reference ....................................................................... 28
Clock Input Considerations...................................................... 29
Power Dissipation and Standby Mode .................................... 31
Digital Outputs ........................................................................... 32
Timing ......................................................................................... 32
Built-In Self-Test (BIST) and Output Test .................................. 33
Built-In Self-Test (BIST)............................................................ 33
Output Test Modes..................................................................... 33
Serial Port Interface (SPI).............................................................. 34
Configuration Using the SPI..................................................... 34
Hardware Interface..................................................................... 34
Configuration Without the SPI ................................................ 35
SPI Accessible Features.............................................................. 35
Memory Map .................................................................................. 36
Reading the Memory Map Register Table............................... 36
Memory Map Register Table..................................................... 37
Memory Map Register Descriptions........................................ 39
Applications Information .............................................................. 40
Design Guidelines ...................................................................... 40
Outline Dimensions ....................................................................... 41
Ordering Guide .......................................................................... 41
REVISION HISTORY
7/13—Rev. B to Rev. C
Changes to Data Clock Output (DCO) Section ......................... 32
3/13—Rev. A to Rev. B
Changes to Table 17.......................................................................... 1
Updated Outline Dimensions ....................................................... 41
1/10—Rev. 0 to Rev. A
Changes to Worst Other (Harmonic or Spur) Parameter,
Table 2 ................................................................................................ 6
Changes to Figure 77...................................................................... 29
Changes to Input Clock Divider Section..................................... 30
Changes to Table 17........................................................................ 37
Updated Outline Dimensions ....................................................... 41
10/09—Revision 0: Initial Version
Rev. C | Page 2 of 44



Analog Devices AD9255
Data Sheet
GENERAL DESCRIPTION
The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter
(ADC). The AD9255 is designed to support communications
applications where high performance combined with low cost,
small size, and versatility is desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The ADC features a wide bandwidth differential sample-and-
hold analog input amplifier supporting a variety of user-selectable
input ranges. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9255 is suitable for applications in communications,
instrumentation, and medical imaging.
AD9255
A differential clock input controls all internal conversion cycles. A
duty cycle stabilizer provides the means to compensate for vari-
ations in the ADC clock duty cycle, allowing the converters to
maintain excellent performance over a wide range of input
clock duty cycles. An integrated voltage reference eases design
considerations.
The ADC output data format is either parallel 1.8 V CMOS or
LVDS (DDR). A data output clock is provided to ensure proper
latch timing with receiving logic.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface. Flexible power-down options
allow significant power savings, when desired. An optional on-
chip dither function is available to improve SFDR performance
with low power analog input signals.
The AD9255 is available in a Pb-free, 48-lead LFCSP and is
specified over the industrial temperature range of −40°C to +85°C.
Rev. C | Page 3 of 44







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