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R5F571MJDDFP Dataheets PDF



Part Number R5F571MJDDFP
Manufacturers Renesas
Logo Renesas
Description 240-MHz 32-bit RX MCU
Datasheet R5F571MJDDFP DatasheetR5F571MJDDFP Datasheet (PDF)

Features Datasheet RX71M Group Renesas MCUs R01DS0249EJ0100 Rev.1.00 240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory, Jan 15, 2015 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface Features ■ 32-bit RXv2 CPU core  Max. operating freque.

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Features Datasheet RX71M Group Renesas MCUs R01DS0249EJ0100 Rev.1.00 240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory, Jan 15, 2015 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface Features ■ 32-bit RXv2 CPU core  Max. operating frequency: 240 MHz Capable of 480 DMIPS in operation at 240 MHz  Single precision 32-bit IEEE-754 floating point  Two types of multiply-and-accumulation unit (between memories and between registers)  32-bit multiplier (fastest instruction execution takes one CPU clock cycle)  Divider (fastest instruction execution takes two CPU clock cycles)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions: Ultra-compact code  Supports the memory protection unit (MPU)  JTAG and FINE (one-line) debugging interfaces ■ Low-power design and architecture  Operation from a single 2.7- to 3.6-V supply  Low power consumption: A product that supports all peripheral functions draws only 0.2mA/MHz (Typ.).  RTC is capable of operation from a dedicated power supply.  Four low-power modes ■ On-chip code flash memory  Supports versions with up to 4 Mbytes of ROM  No wait states at up to 120 MHz or when the AFU is hit, one wait state at above 120 MHz and when the AFU is missed  User code is programmable by on-board or off-board programming.  Programming/erasing as background operations (BGOs) ■ On-chip data flash memory  64 Kbytes, reprogrammable up to 100,000 times  Programming/erasing as background operations (BGOs) ■ On-chip SRAM  512 Kbytes of SRAM (no wait states except in the 256 Kbytes from 0004 0000h to 0007 FFFFh when ICLK is set to 120 MHz or faster)  32 Kbytes of RAM with ECC (single-error correction and double error detection)  8 Kbytes of standby RAM (backup on deep software standby) ■ Data transfer  DMAC: 8 channels  DTC  EXDMAC: 2 channels  DMAC for the Ethernet controller: 3 channels for 176- and 177-pin products; 2 channels for 100-, 144-, and 145-pin products ■ Reset and supply management  Power-on reset (POR)  Low voltage detection (LVD) with voltage settings ■ Clock functions  External crystal oscillator or internal PLL for operation at 8 to 24 MHz  Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz  120-kHz clock for the IWDTa ■ Real-time clock  Adjustment functions (30 seconds, leap year, and error)  Real-time clock counting and binary counting modes are selectable  Time capture function (for capturing times in response to event-signal input) ■ Independent watchdog timer  120-kHz (1/2 LOCO frequency) clock operation ■ Useful functions for IEC60730 compliance  Oscillation-stoppage detection, frequency measurement, CRC, IWDTa, self-diagnostic function for the A/D converter, etc. .


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