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IT8783E/F
Environment Control – Low Pin Count Input / Output (EC - LPC I/O)
Preliminary Specification V0.5 (For A Version)
ITE TECH. INC.
This specification is subject to Change without notice. It is provided “AS IS” and for reference only. For purchasing information, please contact the nearest sales representatives. Please note that the IT8783E/F V0.5 is applicabe to the A version.
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Copyright © 2010 ITE Tech. Inc.
This is a Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous material issued for the products herein referenced. Please contact ITE Tech. Inc. for the latest document(s).
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Revision History
Revision History
Section Table 5-9
Table 5-12 Table 5-16
8.3.11 Table 8-18
Revision
Pin Description of Serial Port 6 Signals The power information of the followings was added:
− Pin 85 z RTS6# z GP34 z CIRRX1 − Pin 77 z SOUT6 z GP35
Pin Description of Keyboard Controller Signals The power information of the followings was added:
z GP10-13
Pin Description of Miscellaneous Signals The second function for pin 77 was corrected to #SOUT6.
GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=00h) The default was modified to 00h.
Location Mapping Table GP 60-62 were removed.
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A
IT8783F/E V0.5
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Contents
CONTENTS
1. Features
................................................................................................................................................ 1
2. General Description ....................................................................................................................................... 3
3. Block Diagram................................................................................................................................................ 5
4. Pin Configuration ........................................................................................................................................... 7
5. Pin Description............................................................................................................................................. 11
6. List of GPIO Pins ......................................................................................................................................... 27
7. Power On Strapping Options ....................................................................................................................... 31
8. Configuration .............................................................................................................................................. 33
8.1 Description of Configuring Sequence ............................................................................................... 33 8.2 Description of Configuration Registers ............................................................................................. 35
8.2.1 Logical Device Base Address .............................................................................................. 43 8.3 Global Configuration Registers (LDN: All) ........................................................................................ 44
8.3.1 Configure Control (Index=02h)............................................................................................. 44 8.3.2 Logical Device Number (LDN, Index=07h) .......................................................................... 44 8.3.3 Chip ID Byte 1 (Index=20h, Default=87h) ............................................................................ 44 8.3.4 Chip ID Byte 2 (Index=21h, Default=83h) ............................................................................ 44 8.3.5 Configuration Select and Chip Version (Index=22h, Default=00h) ...................................... 44 8.3.6 Clock Selection Register (Index=23h, Default=00h) ......................................................