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MACH445-15

Lattice

High-Density EE CMOS Programmable Logic

FINAL COM’L: -12/15/20 MACH445-12/15/20 High-Density EE CMOS Programmable Logic Lattice Semiconductor DISTINCTIVE CH...


Lattice

MACH445-15

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Description
FINAL COM’L: -12/15/20 MACH445-12/15/20 High-Density EE CMOS Programmable Logic Lattice Semiconductor DISTINCTIVE CHARACTERISTICS s 100-pin version of the MACH435 in PQFP s 5 V, in-circuit programmable s JTAG, IEEE 1149.1 JTAG testing capability s 128 macrocells s 12 ns tPD s 83 MHz fCNT s 70 inputs with pull-up resistors s 64 outputs s 192 flip-flops — 128 macrocell flip-flops — 64 input flip-flops GENERAL DESCRIPTION The MACH445 is a member of the high-performance EE CMOS MACH 4 family. This device has approximately twelve times the macrocell capability of the popular PAL22V10, with significant density and functional features that the PAL22V10 does not provide. It is architecturally identical to the MACH435, with the addition of JTAG and 5-V programming features. The MACH445 consists of eight PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. The MACH445 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synch...




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