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H5TQ4G83AFR-xxL Dataheets PDF



Part Number H5TQ4G83AFR-xxL
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4Gb DDR3 SDRAM
Datasheet H5TQ4G83AFR-xxL DatasheetH5TQ4G83AFR-xxL Datasheet (PDF)

4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G83AFR-xxC H5TQ4G83AFR-xxI H5TQ4G83AFR-xxL H5TQ4G83AFR-xxJ H5TQ4G63AFR-xxC H5TQ4G63AFR-xxI H5TQ4G63AFR-xxL H5TQ4G63AFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1/ Jan 2013 1 Revision History Revision No. 1.0 1.1 History Official Version Release x8 IDD update Draft Date Oct. 2012 Jan. 2013 Remark Rev. 1.1/ Jan 2013 2 Description The H5TQ4G83AFR-xxC,H5TQ4G63AFR.

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4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G83AFR-xxC H5TQ4G83AFR-xxI H5TQ4G83AFR-xxL H5TQ4G83AFR-xxJ H5TQ4G63AFR-xxC H5TQ4G63AFR-xxI H5TQ4G63AFR-xxL H5TQ4G63AFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1/ Jan 2013 1 Revision History Revision No. 1.0 1.1 History Official Version Release x8 IDD update Draft Date Oct. 2012 Jan. 2013 Remark Rev. 1.1/ Jan 2013 2 Description The H5TQ4G83AFR-xxC,H5TQ4G63AFR-xxC, H5TQ4G83AFR-xxI, H5TQ4G63AFR-xxI, H5TQ4G83AFR-xxL, H5TQ4G63AFR-xxL,H5TQ4G83AFR-xxJ and H5TQ4G63AFR-xxJ are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V +/- 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 9 and 10 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of0 oC~95oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 85 oC) Industrial Temperature( -40oC ~ 95 oC) • JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 1.1/ Jan 2013 3 ORDERING INFORMATION Part No. H5TQ4G83AFR-*xxC H5TQ4G83AFR-*xxI H5TQ4G83AFR-*xxL H5TQ4G83AFR-*xxJ H5TQ4G63AFR-*xxC H5TQ4G63AFR-*xxI H5TQ4G63AFR-*xxL H5TQ4G63AFR-*xxJ Configuration 512M x 8 256M x 16 Power Consumption Normal Consumption Low Power Consumption (IDD6 Only) Normal Consumption Low Power Consumption (IDD6 Only) Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial * xx means Speed Bin Grade Package 78ball FBGA 96ball FBGA OPERATING FREQUENCY Speed Frequency [MHz] Grade (Marking) CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 CL14 Remark (CL-tRCD-tRP) -G7 667 800 1066 1066 -H9 667 800 1066 1066 1333 1333 -PB 667 800 1066 1066 1333 1333 1600 -RD 800 1066 1066 1333 1333 1600 -TE 800 1066 1066 1333 1333 1600 1866 1866 DDR3-1066 7-7-7 DDR3-1333 9-9-9 DDR3-1600 11-11-11 DDR3-1866 13-13-13 2133 DDR3-2133 14-14-14 Rev. 1.1/ Jan 2013 4 x8 Package Ball out (Top view): 78ball FBGA Package 12 A VSS VDD B VSS VSSQ C VDDQ DQ2 D VSSQ DQ6 E VREFDQ VDDQ F NC VSS G ODT VDD H NC CS J VSS BA0 K VDD A3 L VSS A5 M VDD A7 N VSS RESET 12 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 456 7 NF/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP A15 A12/BC A1 A11 A14 456 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 1 23 A B C D E F G H J K L M N 7 89 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.1/ Jan 2013 5 x16 Package Ball out (Top view): 96ball FBGA Package 1 2 3 456 7 A VDDQ DQU5 DQU7 B VSSQ VDD VSS C VDDQ DQU3 DQU1 D VSSQ VDDQ DMU E VSS VSSQ DQL0 F VDDQ DQL2 DQSL G VSSQ DQL6 DQSL H VREFDQ VDDQ DQL4 J NC VSS RAS K ODT VDD CAS L NC CS WE M VSS BA0 BA2 N VDD A3 A0 P VSS A5 A2 R VDD A7 A9 T VSS RESET A13 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP NC A12/BC A1 A11 A14 1 2 3 456 7 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N P R T 1 23 A B C D E F G H J K L M N P R T 7 89 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.1/ Jan 2013 6 Pin Functional Description Symbol CK, CK CKE, (CKE0), (CKE1) CS, (CS0), (CS1), (CS2), (CS3) ODT, (ODT0), (ODT1) RAS, CAS, WE DM, (DMU), (DML) BA0 - BA2 A0 - A15 A10 / AP A12 / BC Type Input Input Input Input.


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