R5F562T6ADFM Datasheet (data sheet) PDF





R5F562T6ADFM Datasheet, 100-MHz 32-bit RX MCUs

R5F562T6ADFM   R5F562T6ADFM  

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DATASHEET RX62T Group, RX62G Group Ren esas MCUs R01DS0096EJ0200 100-MHz 32- bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data register, amplifier, comparator): two units, 10- bit ADC one unit, the three ADC units a re Rev.2.00 Jan 10, 2014 capable of s imultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary channe ls and four single-phase complementary channels or three three-phase compleme ntary channels and one single-phase com plementary channel) Features ■ 32-bi t RX CPU core  Max. operating freque ncy: 100 MHz Capable of 165 DMIPS in op eration at 100 MHz  Single precision 32-bit IEEE-754 floating point

R5F562T6ADFM Datasheet, 100-MHz 32-bit RX MCUs

R5F562T6ADFM   R5F562T6ADFM  
 Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication an d division unit handles 32- × 32-bit o perations (multiplication instructions take one CPU clock cycle)  Fast inte rrupt  Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt  CISC Harvard arch itecture with 5-stage pipeline  Vari able-length instructions: Ultra-compact code  Supports the memory protectio n unit (MPU)  Background JTAG debugg ing plus high-speed tracing ■ Operati ng voltage  Single 3.3- or 5-V suppl y; 5-V analog supply is possible with 3 .3-V products ■ Low-power design and architecture  Four low-power modes On-chip main flash memory, no wait s tates  100-MHz operation, 10-ns read cycle  No wait states for reading a t full CPU speed  64-Kbyte/128-Kbyte /256-Kbyte capacities  For instructi ons and operands  User code programm able via the SCI or JTAG ■ On-chip da ta flash memory  Max. 32 Kbytes, rep rogrammable up to 30,000 times  Eras ing and programming impose no load on t he CPU. ■ On-chip SRAM, no wait state s  8-Kbyte/16-Kbyte SRAM  For ins tructions and operands ■ DMA  DTC: The single unit is capable of transfer on multiple channels ■ Reset and supply management  Power-on reset (POR)  Low voltage detection (LVD) wi








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