74LS76A FLIP-FLOP Datasheet

74LS76A Datasheet, PDF, Equivalent


Part Number

74LS76A

Description

DUAL JK FLIP-FLOP

Manufacture

Motorola

Total Page 2 Pages
Datasheet
Download 74LS76A Datasheet


74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
of the J and K inputs will perform according to the Truth Table as long as mini-
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions.
SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
LOW POWER SCHOTTKY
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD CD
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
LHXXHL
HLXXLH
L L XXHH
HHh h q q
HH l h LH
HHh l HL
HH
l
l
qq
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level
L,l = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
Q
CLEAR (CD)
J
LOGIC DIAGRAM
CLOCK (CP)
Q
SET (SD)
K
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
27
16 K SD Q 15 12 K SD Q 11
1 CP
6 CP
4 J CD Q 14 9 J CD Q 10
3
VCC = PIN 5
GND = PIN 13
8
FAST AND LS TTL DATA
5-1

74LS76A
SN54 / 74LS76A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High
IOL Output Current — Low
54, 74
54
74
– 0.4
4.0
8.0
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
Guaranteed Input HIGH Voltage for
2.0 V All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5
74 2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
J, K
Clear
Clock
J, K
Clear
Clock
20
60 µA VCC = MAX, VIN = 2.7 V
80
0.1
0.3 mA VCC = MAX, VIN = 7.0 V
0.4
IIL Input LOW Current
J, K
Clear, Clock
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20
ICC Power Supply Current
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
–100
6.0
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Clock, Clear, Set to Output
30 45
15 20
15 20
mA
mA
Unit
MHz
ns
ns
VCC = MAX
VCC = MAX
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear Set Pulse Width
Setup Time
Hold Time
Limits
Min Typ Max
20
25
20
0
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-2


Features DUAL JK FLIP-FLOP WITH SET AND CLEAR The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Cle ar inputs. These dual flip-flops are de signed so that when the clock goes HIGH , the inputs are enabled and data will be accepted. The Logic Level of the J a nd K inputs will perform according to t he Truth Table as long as minimum set-u p times are observed. Input data is tra nsferred to the outputs on the HIGH-to- LOW clock transitions. SN54/74LS76A DU AL JK FLIP-FLOP WITH SET AND CLEAR LOW POWER SCHOTTKY MODE SELECT — TRUTH T ABLE INPUTS OUTPUTS OPERATING MODE SD CD J K Q Q Set Reset (Clear) *U ndetermined Toggle Load “0” (Reset) Load “1” (Set) Hold LHXXHL HLXXL H L L XXHH HHh h q q HH l h LH HHh l HL HH l l qq *Both outputs will be HIGH while both SD and CD are LOW, b ut the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L,l = LOW Voltag e Level X = Immaterial l, h (q) = Lower case letters indicate the state o.
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