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HD64180 Dataheets PDF



Part Number HD64180
Manufacturers Hitachi
Logo Hitachi
Description 8-Bit High Integration CMOS Microprocessor User Manual
Datasheet HD64180 DatasheetHD64180 Datasheet (PDF)

IEC I INTEGRATED ELECTRONICS CORP. 2170 Paragon Drive San Jose, Callfomla 95131 (408) 435-1000 HD64180 8-BIT HIGH INTEGRATION CMOS MICROPROCESSOR USER'S MANUAL #U77 ~HITACHI When using this manual, the reader should keep the following in mind: I. This manual may, wholly or partially, be subject to change without notice. 2. All rights reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part ofthis manual without Hitachi's permission. 3. Hitachi will not be respons.

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IEC I INTEGRATED ELECTRONICS CORP. 2170 Paragon Drive San Jose, Callfomla 95131 (408) 435-1000 HD64180 8-BIT HIGH INTEGRATION CMOS MICROPROCESSOR USER'S MANUAL #U77 ~HITACHI When using this manual, the reader should keep the following in mind: I. This manual may, wholly or partially, be subject to change without notice. 2. All rights reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part ofthis manual without Hitachi's permission. 3. Hitachi will not be responsible for any damage to the user that may result from accidents or any other reasons during operation of his unit according to this manual. 4. This manual neither ensures the enforcement of any industrial properties or other rights, nor sanctions the enforcement right thereof. 5. Circuitry and other examples described herein are meant merely to indicate characteristics and performance of Hitachi semiconductorapplied products. Hitachi assumes no responsibility for any patent infringements or other problems resulting from applications based on the examples described herein. October 1985 ©Copyright 1985, Hitachi America Ltd. Printed in U.S.A. TABLE OF CONTENTS 1. HD64180 OVERViEW................................................. 1.1 Block Diagram .................................................. 1.2 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 CPU Architecture. .. ... . . ... . ..... . . .. . ... . . . .... . . ... .. .. . .. . . . . 1.4 I/O Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 5 6 6 2. HD64180 HARDWARE ARCHITECTURE................................ 8 2.1 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 CPU Bus Timing ................................................ 13 2.3 WAIT State Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 2.4 HALT and Low Power Operation Modes. . . . . . . . .. . . . .. . . . . . . . . . . .. 23 2.5 Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 26 2.6 Memory Management Unit (MMU) ............................... 30 2.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36 2.8 Dynamic RAM Refresh Control ................................... 51 2.9 DMA Controller (DMAC) ....................................... 54 2.10 Asynchronous Serial Communication Interface (ASCI) .............. 68 2.11 Clocked Serial I/O Port (CSIIO) ................................... 78 2.12 Programmable Reload Timer (PRT) ............................... 84 2.13 6800 Type Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 89 2.14 On-chip Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..


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